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Populating the Testbank: Experiences within the Electrical and Electronic Engineering Curriculum
Wellington, S. J., Davis, H. C. and White, S. A. (2001) Populating the Testbank: Experiences within the Electrical and Electronic Engineering Curriculum. In: The 5th International Computer Assisted Assessment Conference., June 2001, Loughborough.

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Abstract
e3an is a HEFCE funded collaborative project to develop a network of expertise in assessment issues within electrical and electronic engineering (EEE). A major focus of this project is the development of a testbank of peer-reviewed questions for use both in formative and summative assessment. The resulting testbank will contain thousands of well-constructed and tested questions and answers from which teachers may select questions appropriate to their students' needs. During Autumn 2000, consultants (subject specialists) from the partner institutions met to identify important learning outcomes for their subject specialism, and then produced sets of appropriate questions (and model answers) to assess those learning outcomes.

Specialist consultants were drawn initially from the partner institutions. Subject teams were established and these agreed key curriculum areas and coverage of the testbank for each particular theme. Authors used MS-Word templates to enter their questions, and these templates also required the authors to enter metadata - information about the questions such as the subject the question examines, the level of the question, the type of question, the cognitive skills required, the time expected etc. This information was used in the database to design an interface to allow teachers to select appropriate sets of questions from the testbank. A surprising but pleasing outcome of the work of the subject teams was that there was little disagreement about the required content of the questions and when the questions were reviewed there was agreement about the standard they represented.

QuickFind Code: QF378
Category: Project Design and Development Services
Product Information
Crownhill can handle your PCB layout and schematic capture requirements. With a commitment to high quality and reasonable pricing you receive your completed design on time and within budget. We handle both new designs as well as updating existing boards. Designs may be either a netlist or a hand drawing. All sizes and complexities of designs are welcomed. Multi-layer PCB's, split planes, surface mount (SMT) and through hole are standard. In addition to hand routing of critical signals we use industry standard PCB layout and schematic capture tools to bring your design to reality, in accordance with your specifications. Netlists and existing PCB's created from various tools are supported. You receive check plots, Gerber files (RS274X format), drill file(s), fabrication drawings, assembly drawings and if applicable, schematics and parts list.

To provide a quotation we will require:

the planned PCB overall dimensions (if known)
the total number of component pins (a good estimate is sufficient)
an indication of the component types e.g. 'all conventional thru pin', 'mostly surface mount' etc.
the anticipated PCB type e.g. single-sided, PTH, multilayer etc.
the anticipated PCB type e.g. single-sided, PTH, multilayer etc.
any non-standard requirements e.g. track shielding, multiple ground planes etc.
the time scale required

We can provide you with design schematics, parts lists, and gerber files from existing PCB designs.
You can send us a completePCB and we can recreate the Scematic to Gerber files, NC drill data, parts list and if required a working copy of the original board.
We can also provide scematics and gerber files from your very rough hand drawings
We can populate your circuit boards
We can provide a total solution to have your boards built, from PCB manufacture to fully populating the PCB and post production testing.
PCB PRODUCTION from your design

We also offer Prototype PCB manufacture as a service. We can supply single or double side PCB's on a same day turnaround, or while you wait ( by proir arrnagement). We can also provide multi layer boards upto 12 layers. On single or double sided boards and some four layer boards, CAM files received before 9am by email and paid for by credit card can be despatched as finished PCBs for delivery overnight to any destination on the UK mainland.

For our fast 24hr or "special" while you wait service the following rules apply:

Minumum Charge
￡30.00 for 10sq cm Single sided no PTH rising to
￡40.00 for 10sq cm Double sided with PTH, larger sizes pro-rata, send design files for a quotation
Circuits supplied can be 1 or 2 layer 0.8 or 1.6 mm Fr4 with Plated Through Holes.
Finished in bare copper tracks and pads on both sides.
Minimum track and gap 0.2 mm
Holes can be PTH or NON PTH, as defined in your gerber files or by your written description.
Only top and bottom copper layer files, excellon CNC drill files, and a profile layer file will be used. All other files will be ignored.
Profiles will be cut with a 2.00 mm or 1.00 mm diameter router as a simple single pass
Profiles must be drawn with a single continuous line, the inside or outside can be used as the cutting line, you must specify which. (default is cutting outside).
Internal cut-outs, circles and slots are permissable, please notify us of these or unusual board profiles (Stars or polygon shapes)
Panelisation and step & repeating is allowed
Please include "readme" files & design notes to aide manufacture
Legends in copper are permissable
Note: For this service

No solder resists
No alterations, editing, or additional instructions regarding the circuits may be made after webeing work on your order
No design rule checking is performed by us
Electrical test is not included
No scoring or tabs, unless discussed with us and agreed in advance, your design notes must be acceptable to us.
No gold or other finishes
Minimum CNC drill size is 0.30mm, maximum CNC drill size is 1.5 mm, larger holes are routed

Data must be received by 9am on a working day and we will ship by close of business the same day or following working day, to be agreed when payment is received.

Please check your files with GC-Prevue before submitting them to us.

The maximum number of circuits available is 2 depending on the size of the circuits, but ask us to quote.

Overnight shipping is ￡10.00 within the UK. Please enquire regarding overseas shipping costs.PCB populating costs with SMT

Does anyone know the populating costs associated with having about 70 0603 /
0805 / SOT23 parts, about 6 SOIC parts ranging from 8 to 16 pins, and a 44
pin TSOP IC mounted to one side of a PCB in 500 to 10,000 qty? Until we get
the PCB done, the assembly houses we checked with are not too helpful. Also,
are there any recommended low cost assembly houses, or ones to avoid? S. G. Gagarin1, Yu. A. Teterin1 and Yu. V. Plekhanov1

(1) Institute of Fossil Fuels, Moscow

Received: 25 July 1986

Abstract The results of a quantum-chemical analysis of the activation of the thiophene molecule on the Pt(111) surface attest to a significant decrease in the energy gap between the highest filled electronic states of the metal and the lowest unoccupied molecular orbitals of thiophene. This promotes the dative transfer of electron density to the antibonding orbitals of the reactant and results in the catalytic degradation of the molecule at the C-S bonds under mild conditions. The results obtained are in satisfactory agreement with the data from an experimental investigation of the thiophene/Pt(111) system by the modern methods of the electronic spectroscopy of solid surfaces.
Translated from Teoreticheskaya i éksperimental'naya Khimiya, Method for populating a substrate with electronic components Document Type and Number:United States Patent 7069647 Link to this page:http://www.freepatentsonline.com/7069647.html Abstract:A novel method and placement system are configured for populating a substrate with an electronic component. The placement system has a substrate holding device for receiving the substrate, a wafer holding device above the substrate holding device serving for receiving a wafer holding frame, and a vacuum forceps holding device arranged above the wafer holding device. The wafer holding frame can receive a complete semiconductor wafer divided into electronic components Methods and apparatus for populating electronic forms from scanned documents
US Patent Issued on December 4, 2007


Inventor(s)
Paul A. Viola
Trausti T. Kristjansson
Cormac E. Herley
Kumar H. Chellapilla

Assignee
Microsoft Corporation

Application
No. 10808194 filed on 2004-03-24

Current US Class
382/174 Using projections (i.e., shadow or profile of characters)

Examiners
Primary: Brian Werner
Assistant: David P Rashid

Attorney, Agent or Firm
Westman, Champlin & Kelly

Foreign Patent References
0 905 643 EP 19990300

Abstract Claims Description Full Text

Claims

What is claimed is:

1. A computer-implemented method for populating an electronic form from an electronic image, the method comprising: (a) identifying a size, orientation and position of a first object having any arbitrary orientation within the electronic image; (b) identifying information elements from pixels within the electronic image that correspond to the first object, including identifying text blocks within the first object using optical character recognition; (c) displaying simultaneously to a user fields of the electronic form in a form data area and the identified text blocks in an object data area that is outside of the form data area, which corresponds to the first object, through a graphical user interface, wherein the text blocks are selectable by the user within the object data area through the graphical user interface for insertion into respective fields of the electronic form in the form data area; (d) parsing the information elements into tagged groups of different information types; (e) automatically populating the fields of the electronic form with the tagged groups to produce a populated form and allowing the user to edit the populated fields through the graphical user interface; and (f) providing a visual status indicator adjacent each field of the form data area alerting the user that the field is unfilled and unverified, filled but unverified, and filled and verified, the status being based on the automatic populating and user editing.

2. The method of claim 1 wherein (a) comprises identifying a size, orientation and position of the first object among a plurality of objects within the electronic image.

3. The method of claim 1 wherein (a) comprises: classifying each pixel within the image to produce pixel classification data; defining an image function to process the pixel classification data; dividing the image into sub-images based on disparities in the image function; and processing the sub-images to determine a size, an orientation and a position for each of the objects, including the first object. Other References

NewSoft Presto! BizCard, User's Guide, 2001, NewSoft Technology Corp.
Y. Caron, P. Makris and N. Vincent, “A Method of Detecting Objects Using Legendre Transform”, RFAI Team Publication, Meghrebian Conference on Computer Science MCSEAI, Annaba (Algeria), May 2002, pp. 219-225.
T. Haenselmann, C. Schremmer and W. Effelsberg, “Wavelet-Based Semi-Automatic Segmentation of Image Objects”, Proc. Signal and Image Processing (SIP 2000), Las Vegas, USA, 2000, pp. 1-8.
S. Jehan-Besson, M. Barlaud and G. Aubert, “Region-Based Active Contours for Video Object Segmentation with Camera Compensation”, Proceedings of IEEE Int'l Conference on Image Processing, 2001, vol. 2, pp. 61-64.