PCB Systems Technical Publications Listing
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System Design

System Solutions - Redefining Systems Design for the Electronics Community

Achieving New Levels of Performance, Quality, Scalability, and Affordability!

"Knowledge is the central competitive factor of the future. DDM is the infrastructure 'glue' that holds everything together."

Design environments that are tool-centric rather than design centric present a range of problems such as interoperability issues between electronic design automation (EDA) tools and the inability to support multiple design teams located across the globe. An EDA vendor helps its customers deliver quality product at competitive prices, and at a faster time-to-market than its competitors. This paper discusses Design Data Management (DDM), its role in supporting hierarchical thread-based designs and multiple, remotely located design teams, and how EDA vendors need to address the challenges of satisfying the "Design Anywhere - Build Anywhere" requirements of today's marketplace.

Basic Transmission Lines: Why Use 'Em At All?

Signals traveling down a trace are compared to all other forms of general communication. Reflections from unterminated lines are analogous to echoes in poorly designed rooms. But just as we can acoustically engineer a room, we can electrically engineer a trace to absorb, and not reflect, echoes. The special nature of transmission lines is discussed, as are the special characteristics that are obtained when we design traces to look like transmission lines and then terminate them in their characteristic impedance.

Optimizing Test Coverage - Recommended Design Rules for an X-ray and In-circuit Test Strategy

Today's complex and high node count printed circuit (PC) boards can be difficult to test. To accurately detect, diagnose and repair their manufacturing faults, several manufacturers test these PC boards with multiple types of test systems. This multiple test style environment combines two or more different types of PC board testers. Currently one strategy combines automatic x-ray inspection with a modification of traditional in-circuit testing.

This strategy changes the test department's overall test paradigm, and has significant impacts on design for testability guidelines for these complex, high node count PC boards. New guidelines need to be established to ensure efficient testing of PC boards with automatic x-ray systems, while also preserving in-circuit requirements that persist. These design guidelines can also assist in providing for selective access removal in cases where automatic x-ray systems provide efficient testing capability.

This paper proposes, examines and summarizes new design for testability guidelines for a combined x-ray/in-circuit testing environment. The paper reviews and updates rules to help test and design engineers provide high-yield processes for x-ray inspection and in-circuit test of PC boards. It also presents guidelines which take advantage of this combined test strategy to reduce required in-circuit probing accessibility, redundancy of test across test systems, and maximizing test efficiency while lowering per unit cost of test.

System Issues in Boundary-Scan Board Test

Boards have evolved into complex systems and even collections of interacting systems. Test engineers struggle to find out how these systems are initialized and booted because of poor documentation. While Boundary-Scan (IEEE Std 1149.1) [IEEE93, Park98] is a powerful test tool, test engineers are finding out that yesterday's DFT rules and test approaches may actually be detrimental to successfully testing systems on a board. One culprit is the boot up process of the board and even individual ICs.

Design for Testability - Test for Designability

Designing for manufacturability and testability has been addressed by numerous publications and papers in the past. Some of the proposed guidelines have become obsolete because of technology and test system advances. Others have been difficult to justify and enforce by the manufacturing/test organizations of the enterprise. This paper addresses the essential testability considerations, both physical and logical, and focuses on both the new constraints and the new freedoms of modern manufacturing test in the ever-changing challenge.

How to Get Started in HDI with Microvias

Electronics continue to become denser, smaller and more complex. The drive to produce more hand-held applications is obvious, but "Mother Nature" is playing a big role in determining the other drivers. As chip signal rise-times continue to decrease (due to smaller gate geometries) the resulting signals are more susceptible to interconnect parasitics. Signal Integrity (SI) improves with miniaturization. All these smaller size factors are drivers for HDI with microvias.

Integrated Circuit increases in total gates has required more pins, as well as finer pin pitch. Over 2000 pins on a 1.0 mm pitch BGA is not unusual, as is 296 pins on a 0.65 mm pitch device. The faster rise-times, as well as the need for SI, require an increasing number of power and ground pins. Consequently, this drives the need for more layers in multilayers. Again, this drives the need for HDI with microvias.

This paper goes over the STEPS in deciding if you need HDI-microvias and how to START. Included is HDI Standards, design trade-offs, materials selection, fabricator selection and Benchmarking, test vehicles, HDI reliability, electrical performance, and CAD features for HDI.

ESR and Bypass Capacitor Self Resonant Behavior

In the past...'anti-resonant' peaks have not generally been regarded as an issue. How did we get away with that for so long?" Improvements in bypass capacitor fabrication and assembly techniques have resulted in higher self-resonant frequencies. The results have sparked many debates on how to best take advantage of these higher frequencies and lower ESRs, while other issues (such as anti-resonant peaks) have been largely ignored. This paper explores the effects of lower ESRs, the true value of impedance minimums, and how to obtain better results using more capacitors. Several examples based on various cases are given, each supported by calculations, results, and illustrations. Information on achieving flat frequency responses is provided in detail, with a link where you can download UltraCAD's Bypass Cap Impedance Calculator that was used in the analysis. Detailed analysis, graphs, and results are provided in the appendices.

The Future of PCB Design

Ten years ago, advanced PCB design technologies such as microvias, high-density interconnect (HDI), embedded passives and high pin-count field programmable gate arrays (FPGAs) were mainly available to power users designing bleeding-edge products for global organizations. Not only are these design technologies rapidly making their way into the mainstream design world, they are readily available, affordable and are a primary factor in determining a company's success and profitability.

I/O Designer -- Uniting Disparate HDL, FPGA and PCB Design Flows

Programmable logic devices have become increasingly attractive for new design starts, as complex devices incorporating embedded processors, memory blocks, and DSP functions are now replacing entire ASICs. Design starts using ASICs have plummeted from a high of over 11,000 in 1997 to below 4,000 in 2003 (Source: Gartner Dataquest). This is because FPGA architectures not only provide excellent reprogrammability, reduced risk and lower development cost benefits compared to ASICs, but also enable quicker design turnarounds with a sufficiently competitive edge in the market and minimal compromise in terms of performance.

The Role of DMS in the PLIM Landscape

This paper gives an overview of the Product Lifecycle Information Management (PLIM) landscape, and distinguishes in particular between Product Data Management (PDM) and Engineering Information Management (EIM) systems. It explains where Mentor's Data Management System (DMS) fits in this picture, what its unique value is in the PLIM landscape, and explains how DMS can work collaboratively and be integrated with other PLIM systems.

RoHS - Impact on Electronic Development

By July 1, 2006, all nations that belong to the EU must enact local laws to enforce the realization of the Restriction of Hazardous Substances initiative (Waste of Electrical and Electronic Equipment) of the EU that bans, to a certain degree, several hazardous substances from electric and electronic products in order to enable the recycling of this equipment. With the realization of these actions for environmental protection, the EU has taken a leadership role in the world. But this is just the beginning. There are clear indications that the USA, China and Japan are also working on similar initiatives. But the other areas are far behind the EU in terms of realization because no local or national laws support these initiatives. These other initiatives are not necessarily identical to the restrictions in the EU defined by 'RoHS' and 'WEEE' and it is not clear whether the restrictions in the EU are never going to change in the coming years. Additional hazardous substances could be added to the catalog in future or the defined maximum values could change over time. This means that companies which plan to introduce measures or solutions to the manufacturing of RoHS compliant products that these measure or solutions need to be flexible, expandable and displayed for future needs.

When FPGA I/O Design Becomes a Necessity

Design teams are being forced to implement urgent changes to unite their HDL, FPGA and PCB flows to ensure they do not negate the cost and time-to-market advantages of using programmable logic. This paper details how Mentor Graphics' and Altera's combined flow overcome the challenges of rising device complexities and higher costs when integrating programmable logic devices on the PCB.

Addressing Integration Problems in a Complex FPGA/PCB/High-speed Design Environment Using the PADS Flow

The complexity of the PCB design flow now rivals the IC design process, with design teams facing a multitude of challenges across a variety of disciplines. In integrating FPGAs onto a printed circuit board, PCB designers need to swap pins on the FPGA, schematic designers need a quick means for creating high pin count FPGA symbols, FPGA designers need to pick the I/O standard that has minimal effect on the PCB, and so on. With the enormous amount of critical data flowing between team members, the old methodology of manually sending a netlist over the wall to the PCB designer leaves too many open issues. It also creates a huge opportunity for errors to creep in, often with devastating effects on the end product. This paper discusses how designers and engineers from all realms can work together as a team, using the specialized tools of the PADS? flow to automate, communicate, and complete each step in the process.

Topology Planning and Routing

Learn about the disconnect between the digital design engineer's vision of bus structures on the PCBs and the failure tools to capture and route this vision in an efficient manner.

Fundamentals of PCB Manufacturing

This paper provides a description of the PCB manufacturing process with respect to the Systems Manufacturing Solutions (SMS) product portfolio of the Systems Design Division (SDD). This is the process of taking the bare PCB and adding the various components to it to create an operational PCB.

Leveraging FPGA in PCB System Designs: Optimizing Profit Margin

Any design project that leverages Field Programmable Gate Arrays (FPGAs) to implement system designs has the opportunity to:
Reduce total design cycle time by as much as 50%
Minimize PCB manufacturing costs
Optimize product profit margin
Early adopters of PCB Optimization technology have validated the concept that FPGA package flexibility can deliver substantial business benefits. This white paper documents the impact of decisions made during the design of the FPGA-PCB interface, from the assignment of the PCB signal to the FPGA package pins through their effect on product profit margin.

Getting Started in HDI Fabrication

High-density interconnect (HDI) fabrication is the fastest growing segment of the printed circuit industry. From its simple start in 1985 for Hewlett-Packard's first 32-bit computer (the Finstrate) to today?s large client servers with 36 sequentially laminated layers and stacked microvias, HDI/microvia technologies are the PCB architectures of the future. Smaller component pitches, larger ASICS and FPGAs with more I/O, embedded passives and higher frequencies with shrinking rise-times all require smaller PCB features, driving the need for HDI/microvia. This paper outlines the six simple processes in PCB fabrication that have to be improved in order to successfully build highly reliable HDI/microvia boards. The conclusion of this paper emphasizes the business opportunities and challenges faced by management in starting and developing the HDI fabrication business including the engineering challenges of improving yields.

Passing the Test

With so many different part numbers running through a production facility, it can be difficult to know how well a process is running. One way that the IC manufacturers solve this issue is to measure specific coupons (test structures) on a parametric die that is placed on each wafer in addition to special parametric wafers. Probe stations can be set up at specific process steps to test these parametric coupons and dies to provide feedback as to whether the process is running in bounds. Having a specific coupon that is sensitive to a specific process can signal a process problem before it hurts production. The accumulation of these process effects on design can be measured at final test and should correlate with a specific first-pass yield (FPY) model (more on FPY models can be found in). The coupon methodology can also be applied to PCB manufacturing. There are many parametric analysis and characterization coupons available for PCBs, forming an important part of a quality assessment process. These process coupons cover reliability, end-product, work-in-process, and process parameter evaluations.

Analysis & Verification

Printed Circuit Board Routing at the Threshold: Advanced Technology for the New Millennium

During the past several years, we have witnessed an unparalleled wave of technological innovation, followed by rapid market adoption. Spurred on by global competitive pressures, new product introductions have come fast and furiously. Sustaining this blistering pace means decreasing both the time and cost of product design cycles. To successfully collapse design cycles in this way, manufacturers must achieve a significant increase in productivity -- the holy grail of the technology-driven marketplace. It follows that design tools must also become more productive to facilitate attainment of this goal. This paper discusses the market drivers leading to tool innovations and a few results, including: high-density routing, high-speed design, and PCB design environments.

Board Systems Design and Verification - Redefining Systems Design for the Electronics Community

"You can't afford to be the first to the market with a product that doesn't work!"
Traditional engineering verification methods meant that most problems weren't discovered early in the design cycle, and debugging the problems often resulted in serious delays in getting the product to market. Computer-aided verification and analysis tools have yet to achieve widespread use, but verification is quickly becoming a business issue instead of just an engineering problem. To get boards out faster, we must take existing verification tools and technologies and apply them earlier in the design process --- what is known as a "left shift" --- and apply the concept of virtual prototyping where the entire design is verified using computer simulations. This paper discuses one of many types of verification, signal integrity (SI), how it has been integrated into the design flow, and ways to improve verification tools among all users involved in the design cycle.

Circuit Timing Analysis

Complete board timing verification solutions are available today through symbolic timing analysis. Symbolic timing analysis offers the speed of static timing without the false timing path reports. This paper describes the Mentor Graphics? symbolic timing analysis and verification tool, Tau?, which uses a spreadsheet-based user interface to generate a concise list of relevant timing equations. The use of Timing Models and a description of the workflow using Tau are also discussed.

Unbalanced Tracks and Differential Impedance

"The calculation of the differential impedance of unbalanced tracks is more complicated…because geometrical and electrical symmetry cannot be used."

This paper discusses the effect of track unbalance on the differential impedance value and provides a method for calculating that value. Differential impedance was determined from the capacitance and inductance matrices of the unbalanced tracks, and the results for both edge-coupled microstrip and stripline are given. Several tables and graphs illustrate the variations.

High-Speed Design: The Benefits of Analysis-Driven Routing

"Analysis-driven routing helps you create more robust designs by optimizing layout …which ultimately speeds your time to market."

Most printed circuit board (PCB) designers do not like the aesthetic results of an autorouter and believe that if they were given enough time they could do a better job themselves. However, today’s complex designs and reduced cycle type demand the use of automation wherever possible. New industry developments require the engineering team to make use of true, multifaced, analysis-driven system design in order to compete in a constantly changing environment. This paper provides a brief history of high-speed routing, and demonstrates why traditional and constraint-driven routing systems are too time-consuming for today’s fast-paced design life cycles. Issues arising from delay and crosstalk routing, placement and termination impacts, differential pairs, and decoupling capacitor breakout routing are discussed. Physical and electrical views are provided to illustrate the numerous examples.

Differential Trace Design Rules: Truth vs Fiction

There is no shortage of design rules available when people talk about differential traces on circuit boards. At various times you can hear people argue that there is a need for, or there is no need for, a variety of special rules regarding continuity of ground planes underneath the traces, equal length traces, equal separation between traces, differential impedance control, etc. So let's set the record straight. NONE of these rules are inherently required by the fact that we are using differential signals! But some of them might be required if we are worried about signal integrity issues in our designs. This article looks at these individual types of rules from the standpoint of various signal integrity issues to see when, if ever, they need be applied.

The Developing Technologies of Integrated Optical Waveguides in Printed Circuits

High Density Interconnect (HDI) printed circuits are now being designed in ever-increasing quantities for very high speed applications. The challenge of opto-electronics and integration of photonics into the printed circuit has started to take off. In the next seven years, expectations are that photonic PCBs will grow to a $2.5 billion industry.
This paper looks at the issues, materials and current processes being researched to create this integrated Opto-Electronic Circuit Board by European, Japanese and North American organizations. In addition to reviewing the global players in polymer photonics, this paper will review the current programs of three of the six groups globally:

EOBC-OptoFoil (Univ. of Ulm, Fraunhafer Inst, Daimler-Chrysler, Siemens)

NTT

PolyGuide (Dupont, HP)

University of Texas

TOPCat (NIST, 3M, Goodyear)

JIEP

Pad Capacitance Extraction for IBIS Models

"Higher frequencies, lower voltage swings and faster rise/fall times are strongly required for today's applications."

Pad capacitance has an important effect on IBIS (Input/Output Information Specification) behavior models used in signal integrity simulation. This paper presents a new technique for pad capacitance extraction based on detecting the resonance frequency of a tank circuit, resulting in the calculation of the overall seen pad capacitance.

Several input-output buffer technologies are used to verify this technique. Positive validation results are shown by Spice simulation. The additional validation of a transistor with a single capacitance-voltage equation proves the effectiveness of the proposed technique

Microstrip Propagation Times: Slower Than We Think

Most of us have been using incorrect values for the propagation speed of our microstrip traces! The correction factor for Er we have been using all this time is based on an incorrect premise. In particular, it results in a value for propagation speed that is independent of variations in trace width and height above the reference plane. But the propagation speed for microstrip traces depends significantly on such variations. This article explains why and develops a superior model for estimating propagation speeds and propagation delays for microstrip configurations.

Seizing Control of the Design Process

In today's competitive market, the first company to get differentiated product to market wins. And to engender truly bona fide product differentiation, companies must rely on electronics. This is true regardless of the market in which a company competes, whether that is telecommunications, automotive, computers, or DVD players.

To maximize revenues, companies must address the problems of rapidly increasing product complexity, shrinking market windows, and massive time-to-market pressure. To do this, corporations must manage the complex set of resources required to design and build today's electronic products.

The most important design resources are people. Most electronic products involve teams of people: for system, board, component, and software design; for component and material procurement; for test, and field service; and for subassembly and system manufacturing. These people often work in different geographical locations and typically use different software applications, sometimes running on different hardware platforms. But to produce electronic products, all of these people must collaborate efficiently, quickly, and at a high level of quality.

Who defines the FPGA Interface?

As FPGA packages pass 1000 pins, managing the interface between the FPGA and board becomes a daunting task. This article discusses sharing the interface definition between the board and FPGA design worlds.

Termination Placement in PCB Design

When we use transmission line techniques to control reflections on circuit board traces, we must terminate the lines. Typically we do so with resistors placed at the beginning (series termination) or at the end (parallel or Thevenin termination) of the trace. An interesting question is, "Where do we place these terminating resistors?" The more obvious assumption that we place them "as close as possible" to the end of the trace may not be the best answer. This article looks closely, with the aid of some simulations, at precisely where terminating resistors should be placed, and why.

Integration of Embedded Components within PCB Structures

Electronics companies are seeing an increased use of embedded components in their PCB designs. Embedded components are fabricated into a printed circuit board and allowed on internal and surface layers. There are several factors driving the trend to use of embedded components over discrete components.

Increased functionality of active devices has the number of passive components growing. The number of discrete passive components is, in many cases 70 to 80% of the total part count and continues to rise as passive-to-active ratios grow. While active devices are being packaged into large pin Ball Grid Arrays (BGAs) the ideal surface placement space for discrete passive components becomes more difficult to obtain.

Also, increased numbers of capacitors are needed as device speeds and digital content increases. Capacitors must be placed close to the IC pin to avoid unacceptable noise or timing delays. Eliminating discrete passive components from the surface layers and embedding them, thus frees surface space and allows the passive devices to be closer to active pins.

Embedded passive components allow for higher frequency (faster) PCBs. The linearity of signals through embedded passive components reduces inductance of "core to surface, return to core" signal paths. Along with lower inductance, embedded passive components can lower power system impedance and radiated emissions - improving the overall electrical performance of a PCB. Also, reliability of the PCB is improved through reducing the overall number of solder joints.

For leading-edge companies, there is also the need for embedded active devices. While additional surface space is made available for other active devices, embedded active devices are not packaged, leading to smaller footprints for the active device. The driving factor to use embedded active devices is reduction in the PCB size format while increasing the active functions.

The Benefits of FPGAs: Are they consumed by the obstacles of integrating FPGAs on a PCB?

FPGAs have proven to be a valuable technology in today's electronic industry, offering performance, time-to-market, and cost advantages. Evidence of their pervasiveness is the fact that almost every Printed Circuit Board (PCB) now contains at least one FPGA. But, does the process of putting the FPGA on a PCB compromise those highly valued benefits? This paper examines the move from ASIC to FPGA technology, and the impact of FPGA on board integration today.

What You Lose From a Lossy Line

Lossy transmission line effects dominate signal integrity at clock frequencies above about 1 GHz and interconnect lengths above about 12 inches. An ideal lossy transmission line model is required to predict the effects of rise time degradation, ISI, collapse of the eye diagram and deterministic jitter. With a flexible simulation tool, design and material selection decisions can be made early in the design process to optimize the balance of cost and performance in high speed digital systems.

Advanced Routing Techniques: The Importance of Timing

Designers no longer have the large timing margins they once had when chip delays consumed the bulk of overall timing budgets. Since then, timing margins were generally sufficient in almost all cases. Die sizes and component geometries have decreased and the propagation delays through these devices have diminished significantly.
With this trend has come a dramatic increase in clock rates used at the board level. The technologies for creating the majority of printed circuit boards, despite the adoption of many manufacturing innovations, has remained mostly unchanged. The decrease in interconnect delays due to board size has not come on the same order of magnitude as the shrinking and increased clock speeds prevalent in the many components in use today. As a result, board level interconnect delay accounts for a much larger percentage of the overall timing budget, which has resulted in a dramatic decrease in the overall timing margins of designs.
Incorporating accurate timing margins under extreme conditions, and understanding specific timing sensitivities in the circuit, ensures robust system operation. Eliminating timing problems as early in the design cycle as possible reduces-and may even eliminate-multiple design iterations and costly rework.
This article explores device-timing alternatives that allow for the most effective combination of devices while ensuring that the design still meets performance goals. We see that using circuit netlists with symbolic timing models provides a repeatable mechanism that easily accommodates circuit connectivity changes, explores device variations and guarantees correct net connectivity during analysis.
Further, symbolic timing allows circuit designers to explore, understand and validate the timing requirements of your circuit. These requirements can drive physical routing to provide a complete timing solution.

Electromagnetic Field Basics

PCB designers, and others who don’t have a lot of background in EMC issues, usually don’t have a good understanding of electromagnetic fields. So electromagnetic fields often get a bad rap. But in fact, they are neither good nor bad, per se. ANY (AC) signal traveling along a trace generates an electromagnetic field. It is the effect of this field that can be good or bad. This article looks at the basic concepts of EMI, EMC, crosstalk, inductance, ground bounce, and RF communications and shows how they are all interrelated. The article also shows why there only a relatively few PCB design rules we have available to us for controlling the signal integrity issues related to electromagnetic field radiation, but why those rules can be effective.

Adjusting Signal Timing (Part 1) by Douglas Brooks

It is becoming a routine requirement for PCB designers to tune traces on boards. Such tuning can be relative (i.e. traces are equal length) or absolute (i.e. traces must be a proscribed length.) This article, Part 1 of a two-part series, addresses why traces need to be tuned at all, how to determine signal propagation speeds and times so that proper trace length can be determined, and how sensitive propagation time (and therefore tuning) is to factors such as Er, trace length, trace pattern, etc. The special case of differential traces is mentioned, and some examples of tuning on a high-speed computer motherboard are illustrated.

Minimize EMI Emissions with Optimum Termination Strategy

Reducing emissions in order to meet the various regulatory standards is often unnecessarily painful. Only a few decent books (and many poor ones!) have been written to help the design engineer optimize the design so that the equipment operates as intended, and also meets the EMI emissions standards.

Unfortunately, meeting these standards often seems to require the addition of complex filters, gasket material, and other expensive components to the system. Since locating the exact path the emissions take to exit the enclosure is difficult, due to the complex nature of the electromagnetic interactions, EMI reduction is often treated as ''magic' and rules-of-thumb are blindly applied. Unfortunately many of these rules-of-thumb were developed for older technology, and do not necessarily apply to the current design activity.

Adjusting Signal Timing (Part 2) - Crosstalk effects in serpentine traces

When a signal passes through a serpentine trace with coupling between the legs, there is an apparent speed-up of the signal. That is, the signal appears to pass through the serpentine section faster than the trace length would otherwise indicate. This apparent speed-up is caused by crosstalk coupling between the legs of the serpentine traces. The amount of apparent speed-up is directly related to the coupling strength between the legs and inversely related to the rise time of the signal passing through the section. The apparent speed-up of the signal is not directly related to the coupled length. For long coupled lengths (those longer than the critical length) signals may become distorted as they pass through the serpentine section, but the degree of distortion is a complex function of the frequency of the signal. Signals pass relatively undistorted through short coupled serpentine sections.

Determining Deterministic Jitter

In synchronous, clocked systems, which include 99% of all high speed digital products, a series of operations needs to happen within one clock cycle. These include all the gate-switching delays within one logic depth, the intra-chip propagation delays, the inter-chip propagation delays, the rise time or charging delays from the interconnects, the set up and hold times, and the skews between the clock and data lines. The timing budget allocates how much time is assigned for each source of delay.

Controlling Impedances When Nets Branch Out

It is not uncommon for a driver to drive numerous receivers. In some designs it is impractical, or undesirable, to drive every receiver from a single trace segment. In such cases it is common to design a trace that branches out into two or more branches, each serving a select number of receivers. The question then becomes where to place the branch point. Improper placement of the branch point can have serious implications from an impedance discontinuity standpoint, resulting in reflections that can have signal integrity consequences. This paper describes several ways to deal with the branching problem in designs if they come up.

Calculation of PCB Track Impedance

"Early methods for calculating impedance can now be used on desktop PCs...the accuracy is as good as, if not better than, the published algebraic equations."

This paper examines the origin of equations used to evaluate controlled impedances, and updates the method of calculation for use with today's personal computers. Several examples are provided, including characteristic impedance for surface microstrip, stripline single track and centered track, and coplanar coupled centered tracks. Numerical principles and results are described, and practical results are given.

3.125 Gbps with your Hair on Fire - Simulation-Based Signal-Integrity Analysis of Digital Interconnects at Multi-Gigabit Speeds

As clock frequencies and data rates soar, system designers are being forced to account for the effects of degraded high-frequency signals, causing otherwise healthy signals to be potentially unrecognizable at receiver ICs. This technical paper will focus on simulation-based signal-integrity analysis of multi-gigabit interconnects using Mentor Graphics' HyperLynx? GHz product. Techniques will be presented for using both HSPICE and IBIS buffer models in concurrent simulations; along with eye-diagram and jitter analysis using multi-bit stimuli, while accounting for line loss, inter-symbol interference, and advanced via modeling.

Crosstalk, Part 1 - Understanding Forward vs. Backward

Crosstalk can be a difficult phenomenon for PCB designers to grasp, particularly since there are two types of crosstalk, forward and backward, which behave quite differently. Although the magnitude of forward crosstalk increases as the length of the coupled region increases, its pulse width remains nearly constant and independent of the length of the coupled region. Backward crosstalk, on the other hand, has a nearly constant magnitude that is independent of the length of the coupled region (as long as the coupled region is "long enough"). But its pulse width is twice as long as the coupled region. This article is Part 1 of a three-part series on crosstalk.

Crosstalk seems to be one of those concepts that confuses many PCB designers. It does have some subtle aspects to it, and it can be a serious problem in some designs. But even more serious, it has some very subtle effects that are hard to recognize. This article, and others to follow in this series, discuss these effects and is intended to help PCB designers understand this signal integrity problem.

Crosstalk, Part 2 - Understanding Forward vs. Backward

It is known that forward crosstalk increases (for all practical purposes) with increasing coupled length, but has a pulse width that is constant. Backwards crosstalk, on the other hand, rises quickly (within the critical region) to a constant maximum, but has a pulse width that increases with increasing coupled length. Simulations using HyperLynx? LineSim? show this very effectively and clearly. The tool can illustrate how impedance loading of the victim trace can impact the magnitude, and even the polarity, of the backward crosstalk pulse. HyperLynx also can be used to clearly illustrate how the backward crosstalk pulse is twice the propagation time through the coupled region plus one rise time, how the crosstalk signal is impacted by the relationship between the traces and their reference planes and also with each other, and how an aggressor AC signal's period can interact with the length of the coupled region to create some surprising crosstalk effects.

Passing FCC/CISPR Tests: A method to build it right the first time

This paper outlines a methodology for how to pass the critical FCC/CISPR test the first time. Repeatable success in this arena demands that a series of design tasks be executed in an appropriate manner. The methodology described in this paper outlines the minimum mandatory steps necessary to achieve first-time success.By perfecting methods for signal integrity analysis, proper power-delivery design, return-current control, and crosstalk analysis, your designs will have a high probability of success, thus ensuring that:
Your engineering cycle will become much more predictable.
Your products will be more reliable.
Your overall design time, plus the time into manufacturing, will decrease dramatically.
Problems like "Hardware Software Wars" will be greatly diminished because the hardware will be stable and software developers will not waste time trying to invent test code that can distinguish between a software problem and a hardware problem.

IBIS Modeling of LVDS Buffers

This report provides detailed information on a study of the effects of internal series termination between positive and negative I/O pads in LVDS buffers. Comparisons between IBIS and SPICE simulations are used to emphasize these effects. Different loading conditions and modeling approaches are considered. IBIS modeling approaches for LVDS buffers are presented. Model validation shows the power of these approaches over other conventional techniques.

Crosstalk Coupling: Single-Ended vs. Differential

Crosstalk between traces is a serious consideration in PCB design.Strategies to reduce crosstalk usually involve routing sensitive traces close to their underlying reference planes and/or spreading the traces apart. "How close" and "How far" are decisions typically reserved for the circuit or system design engineer who derives the rules from simulations or "carry-overs" from previous designs.All too often these rules disregard the types of signals (single-ended or differential) being routed. But, if the degree of crosstalk is a function of the types of signals being routed, then, presumably, the layout rules should reflect this.The purpose of this paper is to look at various signal and trace environments and compare them from a crosstalk standpoint. Given a better, more-quantitative understanding of the relative magnitude of crosstalk signals in different microstrip and stripline environments, it may be possible to adjust layout rules more intelligently, thus making more efficient use of board real estate.

What is This Thing Called 'Current'?

The generally accepted definition of electrical current is "the flow of electrons." But some people criticize this definition on the basis that: (1) it cannot explain how current (a signal) flows at the speed of light, (2) it cannot explain how current "flows" across the plates of a capacitor, and (3) it cannot explain how current can be induced in a conductor some distance away. This article shows that these criticisms are not valid. Electron flow, properly understood, can occur at the speed of light, and some of the component laws on which Maxwell's Equations are based are fully capable of explaining the other phenomena.

The Role of DMS in the PLIM Landscape

This paper gives an overview of the Product Lifecycle Information Management (PLIM) landscape, and distinguishes in particular between Product Data Management (PDM) and Engineering Information Management (EIM) systems. It explains where Mentor's Data Management System (DMS) fits in this picture, what its unique value is in the PLIM landscape, and explains how DMS can work collaboratively and be integrated with other PLIM systems.

Addressing Integration Problems in a Complex FPGA/PCB/High-speed Design Environment Using the PADS Flow

The complexity of the PCB design flow now rivals the IC design process, with design teams facing a multitude of challenges across a variety of disciplines. In integrating FPGAs onto a printed circuit board, PCB designers need to swap pins on the FPGA, schematic designers need a quick means for creating high pin count FPGA symbols, FPGA designers need to pick the I/O standard that has minimal effect on the PCB, and so on. With the enormous amount of critical data flowing between team members, the old methodology of manually sending a netlist over the wall to the PCB designer leaves too many open issues. It also creates a huge opportunity for errors to creep in, often with devastating effects on the end product. This paper discusses how designers and engineers from all realms can work together as a team, using the specialized tools of the PADS? flow to automate, communicate, and complete each step in the process.

Topology Planning and Routing

Learn about the disconnect between the digital design engineer's vision of bus structures on the PCBs and the failure tools to capture and route this vision in an efficient manner.

Effective Stackup Design for High-speed Interfaces

Proper stackup design is important because it forms the basis of a successful printed circuit board (PCB) design. Newer ICs today have edge rates in the sub-nanosecond range; the fastest of which are multi-gigabit transceivers that have edge rates of less than 100ps. With such fast edge rates, it is important to tightly control trace impedance to meet signal integrity requirements and have consistent reference planes to meet our electromagnetic compatibility requirements. It is also essential that we explore stackup options so as not to compromise board yields as well as add unnecessary cost to the manufacturing process.

Saving Time with Analog Simulation

The information age continues to drastically change the designs around us. The days are long gone where all electrical design was in the analog designer?s realm. Even though the majority of designs are digital, there is still one corner of the design world that continues to work at balancing voltages and currents to make things happen. Sometimes the analog engineer?s art is performed with only a pencil and a calculator. Others take a breadboard to the lab and work it out there. Many have embraced the virtual breadboard of the spice engine to make their designs sing. Whatever the method used there is pressure to do it faster.

Designing PCBs with High-Speed Constraints: Developing Constraints

Today's high-speed busses, such as PCI-Express, DDR2, and Serial ATA, running at frequencies from several hundred megahertz to beyond a gigahertz, make for tight timing margins. Today's fine-geometry silicon makes for fast edge rates. Today's growing pressure for smaller and cheaper products makes for very dense PCB layouts. All of these factors necessitate high-speed analysis, and the subsequent generation of routing constraints, in order to implement a successful high-speed PCB design.

Fundamentals of PCB Manufacturing

This paper provides a description of the PCB manufacturing process with respect to the Systems Manufacturing Solutions (SMS) product portfolio of the Systems Design Division (SDD). This is the process of taking the bare PCB and adding the various components to it to create an operational PCB.

Physical Design

Transmission Line Terminations: It's The End That Counts!

Termination strategies are effective in eliminating, or at least controlling, transmission line reflections. There are five types of termination strategies commonly used with transmission lines (parallel, AC, Thevenin, Series, and Diode.) This paper looks at each strategy and summarizes its strengths and weaknesses. In addition, simulations are illustrated for two of tem (AC and Series), helping to illustrate their unique characteristics.

Propagation Times and Critical Length: How They Interrelate

Signal propagation speed is directly related to the relative dielectric coefficient of the material(s) surrounding the signal trace. Traces are considered short, from a reflection standpoint, if the signal can travel to the end of the trace and return to the driver in a time period shorter than the rise time of the signal. Long traces are those where the round trip propagation time is longer than the rise time. In our industry, the critical length, the length where we need to consider using transmission line design and termination techniques, is generally considered to be the length where the round trip propagation time of the trace equals the rise time of the signal.

The Basics of PCB Design

PCBs are not so simple anymore

Printed circuit boards (PCBs) are at the heart of the modern electronic packaging found in almost every consumer electronics product. When designed correctly, PCBs bring predictability, making mass reproducibility possible by minimizing wiring lengths, controlling signal integrity issues, and simplifying troubleshooting and repair issues.

But good designs don't just happen. Many of today's PCBs push, if not exceed, the limits of classic board design. Issues that were once important only in bleeding-edge electronics (such as microvias, high-density interconnects, embedded passives, and high-pin-count FPGAs) now complicate even mainstream PCB development.

This article examines the basics of PCB design, the seven-step process for creating a PCB, and the design challenges faced by companies investing in PCB design solutions.

Simultaneous Design Technology: A Revolution

New software technology has been developed that enables effective parallel design of a circuit board. This technology enables multiple designers, processes and heterogeneous tools to work on the same design database simultaneously and achieve significant gains in design productivity. But, unlike classical divide - and conquer methods that break down a design into pieces and operate on them independently, this new technology enables concurrent progress on a common database, automatically synchronizing changes and resolving conflicts - a first in the EDA industry. This paper focuses on the methods and applications of new parallel design technology that offers a novel paradigm for circuit board design. Topics include:
Review of design problems and concurrent methods
Parallel design architecture
Applying the parallel design technology to:
Layout
Autorouting
Circuit and Board Design
System Design

TeamPCB: The Next Paradigm Change Begins

Everyone in the electronics industry is looking for ways to increase productivity, reduce costs and shorten time-to-market. Processes have been reviewed and tweaked over and over, and serial methods of round-the-clock and round-the-world design of large boards has become popular again. Since PCB software vendors heralded design reuse and variants tools in the early-to-mid 1990's breakthrough methodology adjustments or paradigm changes that can enable dramatic productivity improvements have not been unveiled. It seems as if just keeping up with new manufacturing technology and high-speed requirements has kept EDA vendors fully occupied-until now. The Systems Design Division of Mentor Graphics delivers TeamPCB and a series of other new products this year.

TeamPCB is available as an add-on option for Board Station and Expedition PCB , running on Windows and Unix platforms.

Electronic Product Development in the Global Enterprise

Challenges faced during the design of electronic products can
be broken into technical and business categories. This article offers
solutions to business challenges where the focus is on reducing product
costs and development time.

The Role of DMS in the PLIM Landscape

This paper gives an overview of the Product Lifecycle Information Management (PLIM) landscape, and distinguishes in particular between Product Data Management (PDM) and Engineering Information Management (EIM) systems. It explains where Mentor's Data Management System (DMS) fits in this picture, what its unique value is in the PLIM landscape, and explains how DMS can work collaboratively and be integrated with other PLIM systems.

Distributed Autorouting Using XtremeAR

Learn about XtremeAR process flow for faster autorouting of PCBs by connecting multiple workstations working together, real-time, on the same design. This process can be used as the ultimate team design environment. Faster results can lead design teams to try different routing options to find the optimum route strategy. This paper covers system setup, the required environmental variables and the necessary licenses to start the XtremeAR session. It also describes the strategies for session controls through the XtremeAR client Manager, XtremeAR recording/playback & the performance analysis for XtremeAR session.

RoHS - Impact on Electronic Development

By July 1, 2006, all nations that belong to the EU must enact local laws to enforce the realization of the Restriction of Hazardous Substances initiative (Waste of Electrical and Electronic Equipment) of the EU that bans, to a certain degree, several hazardous substances from electric and electronic products in order to enable the recycling of this equipment. With the realization of these actions for environmental protection, the EU has taken a leadership role in the world. But this is just the beginning. There are clear indications that the USA, China and Japan are also working on similar initiatives. But the other areas are far behind the EU in terms of realization because no local or national laws support these initiatives. These other initiatives are not necessarily identical to the restrictions in the EU defined by 'RoHS' and 'WEEE' and it is not clear whether the restrictions in the EU are never going to change in the coming years. Additional hazardous substances could be added to the catalog in future or the defined maximum values could change over time. This means that companies which plan to introduce measures or solutions to the manufacturing of RoHS compliant products that these measure or solutions need to be flexible, expandable and displayed for future needs.

Addressing Integration Problems in a Complex FPGA/PCB/High-speed Design Environment Using the PADS Flow

The complexity of the PCB design flow now rivals the IC design process, with design teams facing a multitude of challenges across a variety of disciplines. In integrating FPGAs onto a printed circuit board, PCB designers need to swap pins on the FPGA, schematic designers need a quick means for creating high pin count FPGA symbols, FPGA designers need to pick the I/O standard that has minimal effect on the PCB, and so on. With the enormous amount of critical data flowing between team members, the old methodology of manually sending a netlist over the wall to the PCB designer leaves too many open issues. It also creates a huge opportunity for errors to creep in, often with devastating effects on the end product. This paper discusses how designers and engineers from all realms can work together as a team, using the specialized tools of the PADS? flow to automate, communicate, and complete each step in the process.

Topology Planning and Routing

Learn about the disconnect between the digital design engineer's vision of bus structures on the PCBs and the failure tools to capture and route this vision in an efficient manner.

Rethinking Reuse

The promises of board-level design reuse have gone largely unfulfilled. While often cited as the optimal way to address shorter design cycles, implementing an effective design reuse strategy has eluded many design teams. However, there are many aspects to design reuse that can be put into practice to reap significant gains in design time and quality. This article describes several approaches to design reuse, from creating simple variants to reusing entire physical implementations.

Fundamentals of PCB Manufacturing

This paper provides a description of the PCB manufacturing process with respect to the Systems Manufacturing Solutions (SMS) product portfolio of the Systems Design Division (SDD). This is the process of taking the bare PCB and adding the various components to it to create an operational PCB.

HDI Layer Stack-ups for Large Dense PCBs

With the significant increase in IC and FPGA package pin counts and densities, using classical throughhole technology is resulting in an explosion of PCB layer counts and, thus, an explosion in product costs and size. Utilizing High Density Interconnect (HDI) and microvias can successfully break out of these dense BGA packages and reduce PCB layers and size-provided that you use the correct HDI/microvia configurations and the proper PCB layout tools. This paper discusses the various HDI technologies and the best approaches to ensure success.

Topology Planning and Routing - Combining the Expertise of the Designer with Auto-routing Speed

The routing of bus structures on a PCB has always required a manual process to achieve the maximum densities and esthetic look. Also, the communication of the ideal bus topologies (form, layers, nets) has always been done by paper. Mentor Graphics has developed revolutionary technology that enables bus structure topologies to be planned as an automated part of the design process, captured in the design database and then carried on to the physical design process where an auto-router can efficiently route the buses. The result is a process that combines the expertise of an experienced designer with the speed of auto-routing resulting in significant productivity and design cycle time improvements.

Embedded Passives - Tradeoffs and Efficient Design Solutions

The need for many capacitors and resistors to support today's high density, high performance ICs and FPGAs has led to an increase in product sizes due to the space required for the discrete components. Embedding those components on the inner layers of the PCB (embedded) can significantly reduce product sizes and improve performance. This paper discusses the various materials, manufacturing approaches and cost advantages of using embedded passive technologies, and, the tools and approaches required to efficiently design these components.

Data Management

QPaRTS QuickUse Part Request and Tracking System

Many companies are challenged by the complexity of board system library parts management, the increased design cycle time and product costs encountered due to inconsistent quality of library data, and time spent to overcome poor communication between engineering and the library development team. Electronic part views, including logic symbols, simulation models, and physical geometries, that are used during product development in many Electronic Design Automation (EDA) tools must be consistently created to a rigid specification. When the EDA tools are launched on a design and find invalid references to library part data or missing properties, design activities will stall until the problems are corrected. The repetitive nature of rechecking and fixing individual parts creates a bottleneck in library throughput and adds significantly to design cycle time.
Mentor Graphics has combined its expertise in library management methodology with the new QuickUse Part Request and Tracking System, or QPaRTS, to employ solutions that enable library management teams to follow robust correct-by-construction processes for library part life-cycle management, from part request to part obsolesence. QPaRTS interfaces with Mentor Graphics design and library management tools to yield high-quality parts that are proven to function properly before release for engineering use. Automated process measurement facilities enable managers to track volume, cycle time, defect rates, and other metrics in order to continuously improve the overall process. QPaRTS enables designers to monitor the status of library part development and receive immediate notification when parts are complete.

Data Management for Electronic System Design Environment

"An integrated client/server database is used as both an information source and an exchange platform..."

This paper discusses methods for shortening design cycles, collaborative design, and the need for a master database accessible by all team members. Exchange channels needed to connect workgroup and desktop environments are described, and ways to facilitate synchronization and updating processes are given. This object-oriented approach to managing part, library, and product data allows for sophisticated control and coordination of design information.

Web-Based Part Development

"Efficient, accurate EDA library?for design-anywhere, build-anywhere methodology."
This paper explores the universal need for a web-based part development system that would make searching for and gathering reliable information easier and faster. This paper describes the principles behind a web-based part development system, and explains where such a system would fit in the overall design workflow.

Design Data Management for Multi-Site, Multi-EDA Tool Organizations

This paper describes the Mentor Graphics Data Management System (DMS) program for the collaborative Product Definition management (cPDm) market, the challenges this program faces, and ways that these challenges have been met. Major DMS functions are discussed, and summaries from DMS installations are included. Also included is an Executive Summary, information on the DMS core functionality, program and product assessments, DMS success stories, and user information.

ODA Table Symbol Reference Guide

"We believe that the use of table symbols will become much more widespread...especially as pin counts increase."

This paper describes table symbols and their usefulness in High Pin Count Devices (HPCDs), particularly in enhancing readability and structure in printed schematics. Examples of simplified printed schematics and different methods for creating HPCD symbols are provided. Steps describe how to automatically map the PDB, and generic naming shows how to save valuable time when designing high pin count devices. Pre-defined and user-defined options and templates available from the 2002 ODA Library for Mentor Graphics Expedition are discussed, along with tips and examples for using each. Steps and examples provide a workaround for the common problems encountered when changing a pin name on a symbol. Alternatives to the power and ground connection symbols found in the 2002 ODA Library for Mentor Graphics Expedition show how to prevent interference with adjacent lines, and examples of using buses with the table symbols are also provided. As a reference, the naming convention for table symbols in the 2002 ODA Library for Mentor Graphics Expedition is shown.

ODA Central Library Reference Guide: Symbols

"[Implementing] naming conventions that are easy to recognize and use…[making] storing and finding symbols within the library very easy."

This reference guide details the differences between the ODA Master Library and the standard Mentor Central Library. Several procedures for using the ODA Master Library are explained, including setup, schematic symbols, cells (PCB footprints) including padstacks, and PDBs. The use of symbols in the library is explained, as are symbol partitions and symbol naming conventions. Detailed information on creating symbols is provided, and instructions for editing existing symbols are provided. There are numerous examples, including graphics and tables, which illustrate how to create and modify symbols. Finally, portions of two ODA symbol libraries have been included to provide further information and examples.

The Role of DMS in the PLIM Landscape

This paper gives an overview of the Product Lifecycle Information Management (PLIM) landscape, and distinguishes in particular between Product Data Management (PDM) and Engineering Information Management (EIM) systems. It explains where Mentor's Data Management System (DMS) fits in this picture, what its unique value is in the PLIM landscape, and explains how DMS can work collaboratively and be integrated with other PLIM systems.

Topology Planning and Routing

Learn about the disconnect between the digital design engineer's vision of bus structures on the PCBs and the failure tools to capture and route this vision in an efficient manner.

Fundamentals of PCB Manufacturing

This paper provides a description of the PCB manufacturing process with respect to the Systems Manufacturing Solutions (SMS) product portfolio of the Systems Design Division (SDD). This is the process of taking the bare PCB and adding the various components to it to create an operational PCB.

Board Station

HDI Layer Stack-ups for Large Dense PCBs

With the significant increase in IC and FPGA package pin counts and densities, using classical throughhole technology is resulting in an explosion of PCB layer counts and, thus, an explosion in product costs and size. Utilizing High Density Interconnect (HDI) and microvias can successfully break out of these dense BGA packages and reduce PCB layers and size-provided that you use the correct HDI/microvia configurations and the proper PCB layout tools. This paper discusses the various HDI technologies and the best approaches to ensure success.

Expedition Enterprise

HDI Layer Stack-ups for Large Dense PCBs

With the significant increase in IC and FPGA package pin counts and densities, using classical throughhole technology is resulting in an explosion of PCB layer counts and, thus, an explosion in product costs and size. Utilizing High Density Interconnect (HDI) and microvias can successfully break out of these dense BGA packages and reduce PCB layers and size-provided that you use the correct HDI/microvia configurations and the proper PCB layout tools. This paper discusses the various HDI technologies and the best approaches to ensure success.CONFERENCE PROGRAM: CLASSES
***Please note that this is the conference program for PCB West 2007 and is being given as a point of reference for the types of courses presented at the PCB Design Conferences. Please check this site at a later date to see the 2008 conference program.

Conference Intro | Conference Program | Speaker Bios

Sunday and Monday | Sunday | Monday | FREE Tuesday | Wednesday | Thursday | Friday

SUNDAY AND MONDAY, MARCH 25

Sunday, March 25, AND Monday, March 26, 9 am - 5 pm
DEC 1 - High-Speed Design—Signal Integrity, EMI and Crosstalk
Speaker: Rick Hartley, L-3 Communications, Avionics Systems
Attendees: PCB designers, engineers and managers interested in learning and applying high-speed concepts to electronic products.

This two-day course is a compete introduction to the high-speed design concepts needed to ensure success with designs utilizing the fast and ultra-fast ICs of today and tomorrow. In today’s printed circuit boards, it’s not so much the rate at which the circuit is clocked, but the output edge rate (rise/fall time) of ICs that causes signal integrity problems, EMI and crosstalk. The course will cover circuit parasitics, high-frequency currents, signal and wave propagation, propagation time and velocity, control of signal crosstalk, power distribution and decoupling, types of EMI, source control of EMI, control of EMI coupling, split planes and plane islands, PCB layer stackups, filters and filtering techniques, system RF shielding and grounding, metal vs. plastic enclosures, slots in enclosures, and conducted EMI filters. Attendees will learn about interfacing with the fabricator, PCB fabrication methods and concerns, PCB fabrication drawings, impedance testing, test coupons and cost differential of controlled impedance PCBs.

Sunday, March 25, AND Monday, March 26, 9 am - 5 pm
DEC 2 - PCB Design 101
Speakers: Gary Ferrari, Firan Technology Group; and Susy Webb, Fairfield Industries
Attendees: Entry-level PCB designers and anyone else interested in an introduction to PCB design.

Managers often ask, “Where can I send my entry-level designers to learn the tricks of the trade?” This tutorial is the answer! Technical sessions at conferences often emphasize the latest techniques and technologies, but unfortunately those classes are usually too in-depth for the typical novice designer. This class is targeted at the entry-level PCB designer or someone just starting out in this profession. Attendees will begin with the components and the schematic, and continue through layout and post-processing. Attendees will learn how to interpret component specification sheets and schematics, how to plan component placement, as well as routing strategies, DFM, DfT, post-processing and more.

SUNDAY, MARCH 25

Sunday, March 25, 9 am - 5 pm
T1 – Electronics Principles and Signal Integrity
Speaker: Doug Brooks, UltraCAD
Attendees: PCB designers and anyone interested in learning more about signal integrity.

Do inductors and capacitors confuse you? Are you unsure what lead inductance means and why we worry about bypass capacitors? Then this course is for you! We’ll start with an overview of resistors, capacitors, inductors and diodes, and how and why they do what they do. Next we’ll look at what happens to resistance and impedance when we combine these components together in various ways in our circuits. Then we’ll look at how these principles apply to the primary signal integrity issues board designers face today – EMI, crosstalk, signal reflections and transmission lines, and power supply conditioning to prevent ground bounce. At the conclusion of the course attendees will understand the basic causes of these signal integrity problems, and many of their solutions will become apparent.

Sunday, March 25, 9 am - 5 pm
NEW!
T2 – PCB Design for RF Applications
Speaker: Andy Kowalewski, Sychip
Attendees: Any PCB designer who wants a basic understanding of some of the special issues involved in PCB design for radio frequency (RF) applications.

The circuit board is a critical element in the design of RF circuits, and it has its own special characteristics that dramatically affect the way an RF design will function. This one-day workshop will present a practical guide to the many issues facing the modern printed circuit board designer, at a level suitable for the competent board designer facing RF design challenges. The instructor will cover some of the basic RF concepts, including wavelength, frequency spectrum, modulation, power measurement and capacitance, inductance, resonance and impedance. Typical components likely to be encountered in RF design will be reviewed, with discussion of their characteristics and the special care needed in their use. Issues of laminate selection, stackup planning and impedance control will be covered in depth to achieve an understanding of the problems and their solutions. Placement and routing strategies will be discussed in detail, with reference to practical circuits and their special needs when designing for RF applications.

Sunday, March 25, 9 am - 5 pm
NEW!
T3 – Designing for RoHS
Speakers: Gary Ferrari, Firan Technology Group; Doug Sober, Kaneka Texas Corp.; Jo Wynschenk; Rick Love, Cookson
Attendees: PCB design and layout engineers, fabricators, anyone involved in materials selection and final finish specifications for RoHS compliant printed circuit boards.

The dynamics of materials changes and critical assembly considerations for designing RoHS compliant PCBs will be covered in this full day workshop. Industry experts from across the supply chain will provide information on base materials considerations for RoHS, final finish selection and assembly issues that have resulted from the change over to lead free solder pastes and wave soldering.

The program includes an introduction to lead-free design by Gary Ferrari. This overview will provide the attendee with an understanding of the manufacturing and assembly challenges that have resulted from RoHS and lead-free PCB assembly.

Doug Sober will cover material selection for RoHS. One of the most difficult areas for the designer as well as the fabricator has been RoHS compatible material selection. With the increased soldering temperatures and extending contact times, the materials do not behave as expected according to the slash sheets. This session will provide practical guidelines for the selection and qualification of laminate materials used in RoHS compliant PCBs.

The session on final finish compatibility for RoHS assembly by Jo Wynschenk will provide insight into the commonly used final finishes and their typical application based on board type and assembly specifics. The final finishes will be compared for their compatibility with RoHS assembly. The attendee will learn what can be expected from the various final finishes based on design complexity, material type, board thickenss and the specific assembly process.

The workshop will conclude with information on the assembly view of RoHS by Rick Love. Topics to be covered include the impact of lead free on the assembly process, assembly considerations for thick panels and high layer counts, ways to improve hole fill and reduce solder bridging. A key element to successful RoHS assembly is following revised DfA protocols. The session will provide the attendees with useful design guidelines to help prevent and reduce defects in the assembly process will be highlighted.

Sunday, March 25, 9 am - 5 pm
T4 - Design Challenges with HDI/Microvias, Including Hands-On Design
Speakers: Happy Holden, Mentor Graphics, and Mike Fitts, Plexus
Attendees: PCB engineers, designers, managers and others interested in using HDI/microvias.

Part 1 of this course will examine design techniques for the interconnection of area array components from ASIC packaging, portable products, high-performance computing and telecom to dense multichip modules. PCB design rules, materials and selection of PWB structures (blind, buried and microvias) will be examined and compared. The tutorial will define the buried passive technologies, distributed capacitance, HDI technologies, circuit routing guidelines and materials required to permit the use of widely accepted fine-pitch and BGA components. One millimeter, 0.8 mm, 0.65 mm and 0.5 mm fine-pitch components are the focus of pad, spacing and layer assignments. Channel routing techniques using blind vias will show how layers can be reduced by as much as 3X, with the associated cost reductions. Examples will be the 1,247 and 2,577 I/O 1.0 mm CCGAs. Participants are encouraged to bring technical questions for discussion.

Part 2 of this course is a hands-on session. It will take the principles learned in earlier in the course and apply them to real-world designs. Part 2 will begin with a discussion of CAD tool sets and include the use of an actual tool set to strengthen the understanding of how HDI can be used to solve everyday design challenges. Previous tool set experience is required, and the ability to work as part of a team is mandatory.

MONDAY, MARCH 26

Monday, March 26, 9 - 11 am
010 – Current Flow in PCB Traces
Speaker: Doug Brooks, UltraCAD
Attendees: PCB designers and anyone interested in the flow of currents in PCB traces.

We have heard the definition “the current is the flow of electrons.” But there is considerable confusion over flow as a drift velocity of electrons and flow at the speed of light. Also, people wonder how electrons can flow across a capacitor or out through space (EMI). Attendees will learn what is meant by the “flow of electrons” and why that definition (which has been around for 150 years) is still valid. How can there be a propagation delay as current flows, while current is also constant everywhere along a trace, simultaneously? Learn how currents flow down transmission lines, terminated and unterminated, and down differential traces.

Monday, March 26, 9 - 11 am
NEW!
011 – Hands-On Embedded Passive Design for Experienced Designers
Speaker: Mike Fitts, Plexus
Attendees: Experienced designers with previous toolset experience.

How to use a high-end CAD system for parametrically designing with embedded passives. This hands-on experience is with a very specialized tool set provided by Mentor Graphics. The hands-on experience will be instructed using workstations for each participant to go through the design processes. (Depending on the number of attendees, you may be working in teams.) This course will provide attendees with the use of an actual toolset to strengthen their understanding of how buried passives can be used to solve everyday design challenges. This is an advanced class.

Monday, March 26, 9 - 11 am
012 – Designing For Asian Fabrication
Speaker: Happy Holden, Mentor Graphics
Attendees: PCB designers, design managers, layout technicians and others interested in this topic.

If there were ever a time to have a full understanding of DFM, then having your boards built in China is that time! This workshop will highlight the issues, choices, alternatives and conditions that designers need to consider in order to make a printed circuit board manufacturable in Asia, especially China. Attendees will learn how to determine if a fabricator is capable of handling an order; how to use IPC-9151 capability benchmarking to select fabricators; when to control impedance; plating, finishes and thickness distribution; mechanical and image tolerances; materials, multilayer stackup and hole plugging; thieving, plating concerns and why plating thickness varies; calculations vs. 2D field solvers; and much more.

Monday, March 26, 9 - 11 am
NEW!
013 - Are You Ready to Embed Resistors and Capacitors in Your PCBs?
Speaker: Richard Snogren, Bristlecone LLC
Attendees: Anyone interested in embedded passives, but unfamiliar with EP technology.

This half-day course is a review of the state-of-the-art of today’s commercially available embedded passive component materials technology. The course starts with passive component functions and performance drivers to embed passives. This leads into an in-depth discussion of today’s commercial material sets; their electrical and physical characteristics; a useable selection rationale; design, test, and trim tools; and DFM guidelines for implementation. The presentation includes discussion of the relative costs of the various technologies and a methodology for cost analysis. The class concludes with a review of industry initiatives on embedded passive components. What you will learn: Why and when to embed resistor and capacitors; commercially available material sets; design guidelines and manufacturing processes; and embedded passive component industry initiatives.

Monday, March 26, 1:30 - 5 pm
020 – EMI and Crosstalk: Theory, Simulation and Control
Speaker: Doug Brooks, UltraCAD
Attendees: Attendees of this session should have a basic familiarity with PCB design. Engineers who have not had formal training in crosstalk will find this course useful.

Crosstalk is one of the more difficult noise problems for designers to understand and control. And many engineers use rules of thumb that they really don’t understand. This course will first look at forwards and backwards crosstalk to help attendees understand the sources and differences between the two. Then results from an analysis tool will be used to show the strengths and weaknesses behind such tools, and to help the student visualize the crosstalk effects. Finally, some design considerations will be reviewed to show how crosstalk can be managed, minimized, and perhaps even eliminated!

Monday, March 26, 1:30 - 5 pm
NEW!
021 – Intro to Hands-on Embedded Passives Design
Speaker: Happy Holden, Mentor Graphics
Attendees: PCB designers and others with previous toolset experience who are interested in learning how to design embedded passives. It is recommended, but not required, that attendees of this course have also attended “013 - Are You Ready to Embed Resistors and Capacitors in Your PCBs?”

This course is in many ways a continuation of course 013. It will provide attendees with instructions on how to use a high end CAD system for parametrically designing with embedded passives. This hands-on introduction to embedded passives design utilizes a very specialized tool set provided by Mentor Graphics. The hands-on experience will be instructed using workstations for each participant to go through the design processes. (Depending on the number of attendees, you may be working in teams.) This will provide attendees with using an actual toolset to strengthen their understanding of how buried passives can be used to solve everyday design challenges.

Monday, March 26, 1:30 - 5 pm
NEW!
022 – The Routing Workshop
Speaker: Andy Kowalewski, Sychip
Attendees: PCB designers and anyone else with basic PCB physical design knowledge.

This workshop is for anyone wishing to learn handrouting skills or improve their existing routing skills. This presentation will cover designing single-sided assemblies with four-layer board construction and multilayer assemblies with higher layer counts. An abbreviated overall design flow will be followed by a detailed placement and routing strategy. Many specific routing examples will be shown for discussion. General placement and routing tips will be covered throughout the presentation and listed at the end for easy review.

Monday, March 26, 1:30 - 5 pm
NEW!
023 – Flexible Circuit Design
Speaker: Joe Fjelstad, SiliconPipe
Attendees: PCB designers, IC packaging specialists, systems and hardward engineers, and assembly and test engineers.

This course reviews design guidelines, including land patterns, via hole layout and routing, flexible laminate materials (polyimide and polyester), fabrication (including metalization and plating), and assembly, plus special situations that require stiffeners. It will also review major flex standards.

FREE TUESDAY, MARCH 27
All FREE Tuesday sessions are FREE to all conference and exhibition attendees. They are not part of the 3-Day Technical Conference.

Tuesday, March 27, 8 - 9 am
NEW!
Keynote Address - Cross Currents: Where PCB Design Meets ICs and Hardware
Speaker: Henry Potts, Mentor Grphics Corp.

The demands for increasingly competitive products are driving the electronics industry to advanced PCB fabrication technologies, the use of innovative design methods to cut cycle time and reduce product costs, and expansion of design team collaboration outside of the PCB space. Potts will discuss industry trends such as company and market globalization, outsourcing, and new manufacturing technologies. He will cite examples of how the EDA industry is developing new technologies to meet these challenges and specific examples of future development directions both within the PCB design space and extended into IC-to-PCB and electro-mechanical design team collaboration. Henry Potts joined Mentor Graphics in March 1999 as vice president and general manager of the Systems Design Division. He has more than 33 years of experience in the electronic industry, including experience in IC and systems development to serving as president and CEO of a VC-funded startup. He was senior vice president for Hitachi Semiconductor, where he oversaw all marketing and product development activities for microprocessor and embedded products for the U.S. He also has held senior management positions at Motorola, VLSI Technology, Schlumberger and Texas Instruments. Potts has a bachelor’s in electrical engineering from the University of Southwestern Louisiana.

Tuesday, March 27, 9 - 10 am
NEW!
030 – A Spreadsheet-Based Solution for Capturing Today’s Designs
Speakers: Steve Durrill, Cadence Design Systems, and Ken Holman, Motorola
Attendees: Design engineers, managers, R&D engineers, electrical engineers.

Designers struggle to quickly and accurately use these devices in schematics. Designers of highly constrained motherboards, backplanes, and SiPs consistently see a number of problems during schematic design capture including: symbol creation for large pin-count devices, logical function representation with graphical symbols, and limited scope of page editors. To circumvent these issues, design engineers have resorted to spreadsheets, like Excel, for capturing the connectivity of the large devices. They have created custom utilities to create physical netlist from the spreadsheets to drive the layout. However, this approach has problems of no support for associated circuitry, lack of connectivity knowledge, and no mechanism for capturing constraints. This paper will discuss a methodology and a tool for addressing these issues. A use model will be described for a new design capture paradigm using spreadsheets. A Motorola case study will demonstrate the benefits of this approach over the traditional schematic-based design capture.

Tuesday, March 27, 9 - 10 am
NEW!
031 – Team Collaboration Methodology for the Future PCB Designer
Speakers: Glenn Torrance and Peter Cerbonne, Cisco
Attendees: PCB designers and design engineers, design team and program managers and anyone interested in better collaboration in the design process.

This paper will discuss the methodology which allows a team of PCB designers to work concurrently on a design. Partitioning enables the sharing of access to a single database regardless of team proximity. With time to market and team environments becoming more important, today’s PCB designer roles are changing drastically. A case study and a live demonstration will be given so each attendee will have a clear understanding of the benefits of team collaboration and the impact of concurrent design engineering.

Tuesday, March 27, 9 - 10 am
NEW!
032 – Thermo-Mechanical Benefits of Carbon Composite Laminates Embedded in PCB and IC Substrates
Speakers: Alex Mangrolia and Burt Villareal, ThermalWorks New design tools flourish at
PCB Design Conference West
Exhibitors at this year's conference will be showing some of their newest and recently released products. Here is a sampling.

The 12th annual PCB Design Conference West (http://www.pcbwest.com) will be held from March 10 through 14 at the San Jose Convention Center, San Jose, CA. Colocated with HDI Expo 2003, the show covers the design and manufacture of advanced circuits, printed-circuit boards, and semiconductor packaging.

Cimmetry Systems (Cambridge, MA) will display AutoVue 17, an AutoCAD viewing tool that adds online real-time visualization and collaboration for 2-D/3-D CAD, EDA, and office documents. The software, which costs $995 for single-user license, allows multiple users to hold synchronous collaborative review sessions over an intranet, extranet, or the Internet and provides meeting control, coviewing of a document, co-markup, and built-in chat functionality.

Zuken (Westford, MA) will announce Cadstar 3D 4.2, a faster, updated version of its 3-D verification module that allows complex board outlines to be directly imported and exported from mechanical CAD tools and transferred to the company's Cadstar 6.0 PCB design tool suite. The tool eliminates the need for physical prototypes while reducing design time significantly. Pricing is $5,000 per seat.

Zuken's Cadstar 3D 4.2

Altium (Sydney, Australia) will debut its next-generation CAM tool, called CAMtastic DXP. Features include bidirectional support for ODB++, additional DRCs for strengthened data verification, and extensive NC drill/rout features.

A version of the Situs topological autorouter for P-CAD 2002 will also be demonstrated. It will be given free of charge to full-suite P-CAD 2002 customers.

Ohio Design Automation (Nashua, NH) will announce InterComm 5.0 EDA tool, which includes a new EDA neutral file format, foreign language redline markup translations, and a new scalable tool configuration. The tool is priced between $300 and $6,500.

Ansoft (Pittsburgh, PA) will announce Spicelink 5.0, true 3-D, signal-integrity, and parasitic-extraction tool for the design of high-speed devices, such as ICs, pc boards, and IC packaging. The tool consists of multiple electromagnetic solver engines, an easy-to-use drawing tool, and a built-in Spice.

Unique to version 5.0 is a technology for producing accurate, 3-D, distributed models for Gbyte data-rate designs. In addition, the tool can use the power and fast memories of 64-bit Unix computing platforms--delivering a tenfold increase in the size and complexity of the structures the software can simulate.

DDE (Newport Beach, CA) will showcase Supermax ECAD, a layout solution for pc board, MCM, hybrid, and advanced packaging design. The tool offers unique capabilities in designing with embedded passive components.

DDE's Supermax ECAD

--Christina Nickolas

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