Miniaturization of handsets and other wireless devices creates scores of shielding challenges as high-frequency components become more closely spaced. As printed-circuit boards (PCBs) shrink, new electromagnetic-interference (EMI) shielding solutions must provide greater levels of interference suppression, but without significantly adding mass, weight, and cost to a device. Fortunately, a new shielding technology developed by W.L. Gore & Associates called snapSHOT. shield, replaces bulkier soldered approaches with a snap-on metallized thermoformed shell that can be attached to a PCB by means of standard ball-grid-array (BGA) solder spheres.

In understanding the shielding requirements of compact wireless designs, the shortcomings of traditional test methods (mostly based on military requirements) become apparent when applied to battery-powered portable wireless designs. Some test methods, such as ASTM D 49351 for planar shielding and a coaxial cell2 for EMI gaskets, for example were developed to characterize the materials that would ultimately comprise an EMI enclosure. But there remain no formal published test methods to evaluate the shielding effectiveness (SE) of a shield assembled to the PCB of a portable wireless device.

At present, two primary shielding approaches are used in cellular telephones: soldered perforated cans and plated covers with EMI gaskets (Fig. 1). Both try to create a complete shield around the PCB's components to ensure proper electrical performance and comply with regulatory requirements for EMI emissions and susceptance.

The goal of an EMI shield is to create a Faraday cage around the enclosed RF components using the six sides of a metallic box. The top five sides are created using a shielding cover or metal can, while the bottom side is achieved by using the ground plane within the PCB. In an ideal enclosure, no emissions would enter or exit the box. In reality, leaks do occur, such as from holes perforated into soldered cans that allow thermal heat transfer during solder reflow. Leaks can also occur from imperfections along an EMI gasket or solder attachments. Leaks are also possible from the spaces between ground viaholes used to electrically connect the shielding cover to the ground plane.

Shields designed for portable devices must be light in weight and low in cost, but they must also meet demanding mechanical and electrical requirements. Phenomenon such as cavity resonance, aperture radiation, and planar shielding are factors RF engineers face when designing shielding enclosures. The problem is further complicated by the fact that accurate EM field prediction from complicated PCB assemblies, particularly in the near field, is virtually impossible, forcing many engineers to build custom test fixtures to evaluate their designs.

To create the Faraday cage required for proper shielding, a metallic enclosure must be placed around and in close proximity to the components on a PCB. Unfortunately, this may have adverse effects on the performance of the components and the functionality of the circuit, with the greatest concern being enclosure (cavity) resonances at any of the PCB's operating frequencies. To study this, a simple test fixture was designed to mimic the effect of placing a metallic enclosure over RF components. Improve PCB Shielding For Portable Devices
Studies into the shielding effectiveness of different shielding approaches on printed-circuit boards have resulted in a lightweight, thermoformed, BGA-attached solution.

Thomas Clupper | ED Online ID #5430 | May 2003

Another important consideration concerning cavity resonance is the effect on the shielding performance of the enclosure. Since energy inside the cavity is amplified at the resonant modes, it is likely that the shielding effectiveness (SE) would be lowest at these frequencies. As Fig. 4 shows, the SE drops significantly at each cavity resonance (due to the dimensions of the cavity).

The methods for evaluating the effectiveness of PCB shields can be broken into three categories: compliance testing, functional testing, and indirect testing. Compliance testing involves evaluation of the final product given industry-standard test methods and acceptance levels, such as spurious emissions, susceptibility, or electrostatic discharge (ESD). Functional testing involves evaluation according to performance requirements set by the manufacturer. Intercavity shielding, radiation from the antenna back into the receiver (Rx), and phase noise are examples of parameters that would be considered.

The last category, indirect testing, is used when describing shielding products. Methods such MIL G 83528B, ASTM D 4935, and ASTM D 991 are guidelines followed by shielding manufacturers to evaluate their products. These methods can characterize the constituent properties of a shield, but cannot predict the performance in a specific application.

Typical surface-mount-technology (SMT) components suffer minimal levels of radiation, although these levels are not negligible. Predicting the radiation response, particularly in the near field, of typical SMT devices is a formidable task. A first step is to consider the coupling between two microstrip lines that would be used to connect components on the PCB. Short transmission lines, even when close together, exhibit very little coupling. This characteristic can help to develop an inefficient radiator that can be used as a test vehicle (Fig. 5).

Since the dielectric substrate thickness on the outer layers of the PCB is usually very thin, it is desirable to have the radiating element be a separate component, instead of integrating it onto the PCB. The height of a separate radiator can be readily adjusted, while maintaining the height sufficiently lower than the inside height of the shield. By using the remaining dimensions of the transmission-line radiating element (height, length, width, and termination impedance), the response of the radiator can be optimized for testing shields on PCBs.

The special test fixture developed for testing shields on PCBs (Fig. 6) includes a custom-designed SMA connector that, using a solder pre-form, completely seals the launch point to the ground plane of the PCB. The connectors then feed the radiating elements that are attached to the opposite side of the PCB. The shields would then be centered and attached over each of the elements.

The mode-stirred reverberation chamber technique (Fig. 7) is an excellent EMI test method because of its high dynamic range and repeatability.4,5 In this technique, the radiation characteristic from the device under test (DUT) is compared to that of a reference horn antenna. Measurements are first performed on the horn antenna, then the DUT is substituted for the horn and tested. Of course, only one radiator/cavity can be tested at a time. The radiator is first measured without a shield over it, then the shield is attached and the device is re-measured. The SE is calculated as the difference between the received power levels (in decibels) before and after the shield is applied.

The frequency range of such a test is determined by the room dimensions, the test equipment, and the antenna bandwidth. The main limitation is usually the lower frequency boundary, determined by the room size and antenna used. A frequency range of 1 to 13 GHz was used for the tests in this article.

Practically, EMI enclosure cannot be made to be a complete Faraday shield. Gaps due to perforations in the shields, incomplete shields, breaks in the shielding gasket, spaces between grounding vias, and relief areas in the ground plane are necessary to manufacture the complete PCB. But as long as the size of the aperture is much smaller than the wavelength of the highest frequency of interest, it should not cause an appreciable amount of leakage.

The effects of apertures much smaller than a wavelength at the highest operating frequency of interest has been studied to great lengths.9-11 For perforated screens, the formula of Fig. 8 has been used to show the frequency relationship between the size of the aperture and SE. Although this frequency dependence represents an accurate relationship for the far-field response of a large array of holes, an offset factor in SE can deviate quite a bit from real-life applications. To overcome this, a relationship for the far-field (plane-wave) response was derived using empirical data taken from thin copper sheets perforated using the traditional hexagonal pattern. Initially, 1-mm-diameter holes were placed on a 1.7-mm hexagonal grid, such that about 1552 holes fell within the annulus of a typical ASTM D 4935 test cell. The SE was obtained using S21 measurements with and without the sheets in place (Fig. 8).

A simple model was generated to represent this test pattern, using the formula of Fig. 8 and a correction offset factor. The next three test patterns were generated by doubling the spacing between the holes each time. This way, about four times fewer holes fell within the annulus of the coaxial cell for each pattern. To generate the modeled data, the original model was changed by a factor of 4 each time, which yielded 12-dB offsets. As Fig. 8 shows, the frequency relationship follows what would be expected for plane-wave excitation of perforated thin sheets.

The test fixture (Fig. 2) consists of two 50-Œ¸, 0805 resistors that are launched from SMA connectors from the opposite side of the ground plane. The spacing is arbitrarily set at 0.5 in. (1.27 cm) so that minimal coupling would occur between the two components when the shield is not in place (Fig. 3). Coupling was determined from 20logS21 measurements on a microwave vector network analyzer (VNA). A perforated metal square can, with inside dimensions of 1.805 ¡Á 0.114 in. (4.584 ¡Á 0.29 cm), was soldered over the components to illustrate the effects of a metal cavity. The simple formula in Fig. 3 was used to roughly calculate the resonant modes of the EMI enclosure. The formula applies to rectangular cavities and is fairly accurate if the cavity is filled with air. However, most enclosures on PCBs will include the PCB material and components within them, raising the cavity's effective dielectric constant and thus lowering its resonant frequency.

With the shield in place, coupling between the two components is severely increased at and around the resonances, as much as 50 dB for this fixture. Peaks occur at the resonant frequencies calculated by the formula. Below the first resonant frequency, the coupling between the two components is virtually unchanged. Thus, it is critical to consider these resonant conditions when designing EMI enclosures.

A more accurate way to predict the effects of a rectangular cavity involves the use of an EM field simulator, such as the Sonnet. Professional Planar Software Suite from Sonnet Software (Liverpool, NY). This software models planar circuits within a metallic box, and can easily be used to examine the effects of cavity dimensions, substrate material, and metal wall conductivity. (A free version of the software is available on Sonnet's website at www.sonnetusa.com.) Figure 4 shows the response of a model produced by the software, with close agreement to the actual measured data.

Printed circuit boards (PCBs) power everything from portable radios to refrigerator-sized supercomputers, but they remain vulnerable to a simple, heat-induced threat: warpage. A warped PCB may cause a device to stop working. Boards that warp during manufacturing after expensive components are added can mean thousands of dollars in losses.

Now manufacturers have a new weapon against warpage: Thermoir¨Œ., a novel experimental technique developed at the Georgia Institute of Technology and licensed by Electronic Packaging Services (EPS) Ltd., Co. The patented process provides real-time data about PCB warpage, helping manufacturers avoid design problems and save money, said Thermoir¨Œ. developer Dr. Charles Ume.

Dr. Charles Ume (right) and a former graduate student examine the fringe pattern generated when a printed circuit board is heated in the oven Ume developed.

"Electronic packaging companies can use the warpage information to make changes in their PCB design early," said Ume, an associate professor in the School of Mechanical Engineering. "That way, there's no mass production of a product that has a problem."

The heat that can warp PCBs is generated each time we turn on computers, camcorders or other PCB-run devices. Also, temperatures up to 230 degrees Celsius are an integral part of PCB processing.

"In addition, if the PCB is small, thin and also densely populated with components, as is the current industry trend, that is an invitation for warpage-related reliability problems," Ume said.

Noted EPS manager Dirk Zwemer: "It's not uncommon to see losses of one to three percent in a mature product, and it can be much higher for some designs."

Research sponsors, who were brought together through Georgia Tech's Manufacturing Research Center (MARC), include Motorola, MICOM, Ford Electronics, IBM, DEC and AT&T.

For this new process, Ume developed a special oven with a glass grating top, through which the PCB placed inside is visible. A white light shines through the glass grating onto the PCB, and an inexpensive, compact, charge-coupled device camera captures warpage digitally as it occurs.

The flat glass grating is etched with equally spaced parallel lines. It is placed above and parallel to the PCB. A beam of white light is directed onto the glass at a specific angle, causing the etched lines to create a shadow on the surface of the PCB. When the surface of the PCB curves due to warpage, a moir¨Œ pattern is produced by the geometric interference between the etched lines on the glass and the shadow of those lines on the PCB's surface. The more the PCB warps, the greater number of moir¨Œ fringes that appear.

Ume counts the number of fringes, puts them into an equation, and a computer determines how much warpage has occurred. The warpage process is displayed in real time on a television screen and recorded on video and on computer.

Developed in MARC's Advanced Electronic Packaging Lab, the Thermoir¨Œ. technique can be used to simulate the three major kinds of soldering processes -- infrared reflow, convective reflow and wave.

The automated oven system can reproduce any given soldering temperature history used in producing a board, while measuring PCB warpage at any specified time interval or temperature. That means the system can pinpoint which processes or designs may cause the most warping.

Companies can use the results to make design or process changes before production, such as changing soldering temperature profiles, reducing or extending processing times, relocating key components, and changing the types of materials used in the construction of the PCB.

The ability to measure thermally induced warpage also enables manufacturers to validate their numerical warpage predictions, which are created using finite element modeling techniques.

If a certain amount of warpage is allowable, the new technique lets manufacturers measure initial warpage, rather than assuming the board is flat before transistors and other items are added. Manufacturers can then determine how much additional warpage develops during further processing or attachment of components.

Ume's technique also allows warpage measurement of the different materials that are sandwiched together to make a wiring board -- FR-4 laminates, fiber (prepreg), several varieties of copper foil and newly developed materials.

"These are unique measurement techniques, and the electronic packaging industry is very excited about them," Ume said. "Savings in scrap PCBs, rework, down time and loss in market share can run into the millions of dollars."

The research sponsors asked Ume to commercialize Thermoir¨Œ.. With help from Georgia Tech's Advanced Technology Development Center, the EPS Ltd., Co. licensed the technology and began offering help to the electronics industry in August 1994. Georgia Tech is a partner in the company.

Although EPS was formed to help the electronics industry, future Thermoir¨Œ. users could include manufacturers of foil, tape, resin, glass fibers and aviation equipment, said manager Dirk Zwemer. Other possibilities include putting Thermoir¨Œ. on an assembly line and making it more automated for the average worker.

"The technical applications are larger than the original sponsors knew it would be when they started," he said. "We want to be a good example of technology transfer." PCB layout

What this technique is used for

The use of EMC techniques in printed circuit board (PCB) design, placement and layout is one of the most powerful and cost-effective ways to reduce emissions and improve immunity.

For low-frequency analogue devices and circuits which do not have appreciable emissions, these techniques are used to improve immunity.

Good PCB design for EMC can reduce the costs of filters and shielding, reduce the number of development iterations, improve circuit functional performance (improve signal integrity and signal-to-noise ratios), improve time-to-market, and reduce project financial risks.

How this technique is used

From the very first ¨C PCBs should be designed and laid out using a number of well-proven EMC principles.

It is not anything like as cost-effective (or time-saving) if the PCB EMC techniques are applied later on, when EMC problems have been found and solutions are being sought.

Key issues in employing this technique

Circuit segregation or ¡Žzoning¡¯

Firstly the ¡Žoutside world¡¯ and ¡Žinside worlds¡¯ are identified. The ¡Žinside world¡¯ is the area or volume where the designer has control over all EMC phenomena (e.g. by shielding and/or filtering), and the outside world is everywhere else.

Secondly the ¡Žinside world¡¯ is further segregated into subsidiary zones. The traditional segregation between analogue, digital, and switch-mode power conversion circuits is an example of this internal ¡Žzoning¡¯.

All of the devices and conductors in each zone are rigorously separated from all of the devices and conductors in the other zones, to reduce the electromagnetic coupling between them as much as is possible in the space available.

It may be necessary (for EMC cost-saving or signal integrity reasons) to fit shielding over individual zones. Five-sided metal boxes soldered to the PCB¡¯s 0V plane at numerous points can create a fully enclosed shielded box around a zone.

Only the essential interconnections between zones are permitted to cross the boundaries between zones, and any/all of them may need filtering or otherwise suppressing.

Suppressing interfaces between circuit zones

Each conductor that passes from one zone to another may need to be fitted with filters or other suppression devices such as opto-isolators, transformers, transient protection, etc.

This is especially true of the interconnections between the ¡Žinside world¡¯ and the ¡Žoutside world¡¯.

Filters or other suppressers must be located at zone boundaries.

Using 0V and power planes

A PCB plane is a solid sheet of copper, not a fill or a mesh. Fills are useless for EMC but meshes can have some benefit. However, planes produce wonderful results and modern digital processors rely totally on them for signal integrity as well as needing them for EMC.

Through-hole plated (THP) PCBs perforate the planes at every via and component lead, and it is important that the planes ¡Žweb¡¯ between the clearance holes, to avoid the creation of larger gaps and slots where the clearance holes merge with each other.

High-density interconnect PCB technology (sometimes called microvia or build-up technology) allows the use of vias that do not penetrate all the way through a PCB, allowing the planes to perform much better at frequencies above 100MHz.

Effective decoupling

Inductance in the power distribution of a PCB makes it impossible to deliver the fast pulses of current required by digital devices. Local capacitance is therefore required to store enough charge for their ICs¡¯ short-term demands. These ¡Ždecoupling capacitors¡¯ also ensure that the high-frequency noise currents caused by digital device power demands are restricted to small areas of the power distribution, to minimise emissions.

Decoupling has another function, which is to prevent external interference from entering the power pins of analogue and digital ICs. Once inside an IC, RF signals might interfere directly with signals that share their frequency range, or might become demodulated and cause the d.c. bias of the internal circuits to shift, interfering with the functioning of the IC and/or producing unwanted ¡Žbaseband¡¯ noise.

The routing of the decouplers is very important, to minimise inductance and improve their frequency response. Adjacent 0V and power planes in a PCB¡¯s layer ¡Žstack-up¡¯ can be used to provide a distributed decoupling capacitor with an RF performance that is much better than any discrete capacitors.

Very small spacings between 0V-power plane pairs is also an increasing necessity, to provide more decoupling capacitance with better VHF performance. Spacings of less than 0.05mm (0.002 inches) are now being used in some applications.

Transmission Lines

Resonant interconnections make very efficient ¡Žunintentional antennas¡¯ near their resonant frequencies, creating big problems for both emissions and immunity. Transmission line techniques can be applied to all types of conductors, such as cables, as well as to the copper traces on a PCB, to prevent them from resonating, and thus improve the emissions and immunity of their circuits.

By matching the impedance of a signal¡¯s source and/or load to the RF characteristic impedance of the signal¡¯s send and return conductors, digital or analogue waveforms of any practical bandwidth can be communicated whilst maintaining their fidelity, and the interconnection path prevented from resonating.

Routing

The routing of the copper traces on a PCB influences how well they couple electromagnetically to other traces and devices on the same PCB ¨C and also to how well they couple to the conductors and devices (such as EMC testing antennas) in the world outside the PCB.

No traces should ever be routed near to the edge of ¨C or across gaps, holes or splits in ¨C a 0V plane. Also, transmission line traces should never be routed across edges or gaps, holes or splits in power planes.

Some types of signals require traces that do not change layers (except at their ends) and some should be routed between planes and not on the surface of a PCB.

Layer stack-ups

The ordering of the layers (0V planes, power planes, signals) in a PCB is very important. Some types of signal trace are best kept on inner layers, sandwiched between two planes. There should generally be at least one 0V-power plane pair for decoupling. Some signal traces need to be separated from other traces by a 0V or power plane.

Any PCB stack-up with less than eight layers cannot satisfy all of the PCB design-for-EMC principles simultaneously, and so is a compromise. However, for analogue circuits even a two-layer PCB (one layer being a 0V plane) can be very effective at improving immunity; whereas many simple low-speed digital circuits are able to use four layer PCBs and achieve low-cost EMC.

Achieving very small spacings between traces and planes is becoming increasingly important. This requires the trace¡¯s spacing from the plane to be less than the width of the trace.

The cost of the bare PCB is usually unimportant

The EMC design of the PCB is perhaps the most important issue in achieving lowest-cost EMC quickly. However, the resulting bare PCBs themselves will often not be the cheapest.

Many companies still persist in thinking that the most profitable product is the one made from the cheapest components, so they omit EMC considerations from the design of their PCBs if they would have increased the bare-board cost. Unfortunately, this approach generally leads to many costly and time-consuming iterations during development, and to a final product which needs to employ more costly filtering and shielding than it would if its PCB had been designed properly for EMC in the first place.

In other words ¨C skimping on the application of PCB EMC techniques is a false economy.Description

BACKGROUND OF THE INVENTION

This invention relates generally to an improved printed circuit board (PCB). More particularly, this invention relates to an improved PCB having "twisted lends" on the PCB to improve common mode rejection. Still more particularly, this invention relates to an improved PCB having complementary leads located respectively on the solder side and component side of the PCB to improve common mode rejection. The use of printed circuit boards to develop complex circuits having a plurality of components is well known. Such boards are usually substantially planar with a component side and a solder side, to facilitate positioning components relative to the boards and to permit soldering of those components into the circuit to be automated. A bus problem exists with such PCBs, however, in that when a bus structure exists on a PCB for an appreciable distance, the circuit on the PCB is susceptible to cross talk and induced noise from outside interference. Highly accurate circuits are adversely affected by such spurious signals.

One solution that is conventional to inhibit such cross talk and induced noise is to provide the PCB with special shielding. However, such additional structure is costly both from a materials and a labor point of view, and adds to the weight of the circuit. While technically such shielding is satisfactory, its drawbacks generally outweigh its benefits.

Another possible solution is to design into the circuit a common mode rejection circuit which assists in removing such common mode signals and in removing induced noises electronically. However, such additional circuitry is particularly expensive and does not function completely satisfactorily.

Accordingly, it remains an objective in the PCB art to develop a way to encourage a common mode rejection by circuits on the PCB, while inhibiting inducing noise, without the use of complex and expensive additional components of the PCB.

It is known in the electronics art to twist pairs of leads to improve common mode rejection of signals on the respective pair of leads. Such twisting literally occurs physically in that the pair of leads is in fact twisted into an interlaced pattern. It is thus another overall aim of this invention to determine whether such known structure is applicable to PCBs.

These and other aims and objectives of this invention will become apparent to those of skill in this art when considered in light of the written description of the invention which follows taken with the accompanying drawings.

BRIEF SUMMARY OF THE INVENTION

Directed to achieving the foregoing objectives and overcoming problems associated with an elongated bus structure on a PCB, an improved circuit board according to the invention comprises a solder side and a component side, each of which includes an elongated bus structure substantially in register. The bus structure includes a plurality of solder points. Leads are provided between respective pairs of such solder points wherein a high lead is located between a first pair of such solder points on the solder side, and a low lead is located between said first pair of such solder points on the component side and oppositely directed relative to the high lead.

A plurality of patterns for such leads are disclosed.

In providing a common mode rejection circuit on a printed circuit board, the invention in its main aspect comprises a printed circuit board having a bus extending along a predetermined length of a portion of said printed circuit board, the bus having a predetermined width and defining a plurality of openings therein following a predetermined regular pattern, the pattern having at least a first pair of openings positioned on a first lateral side of an imaginary line along the bus, and at least a second pair of openings positioned on a second lateral side of the imaginary line along the boss, the first and the second pairs of openings being relatively arranged so that a first lead interconnecting the first pair of openings is in a twisted pair relationship with a second lead interconnecting the second pair of openings.

The printed circuit board is further characterized in that the first and the second leads are preferably located on opposed sides of the printed circuit board. The printed circuit board has the first lead located on a solder side of the printed circuit board and the second lead is located on a component side of the printed circuit board.

In another aspect, the printed circuit board according to the invention is in combination with the first and the second leads which respectively are soldered at the openings.

The printed circuit board according to another aspect of the invention further includes a plurality of third leads and a plurality of fourth leads respectively in circuit with the first lead and the second lead whereby a plurality of twisted pairs of said first and said third leads are formed relative to said second and said fourth leads.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a representative showing of a portion of a PCB on which the twisted lead invention is placed.

FIG. 2 is a portion of the PCB shown in FIG. 1 showing a plurality of twisted leads on a test PCB as seen from the solder side of the board.

FIG. 3 is a view of the same portion of the PCB as seen in FIG. 2 but as seen from the component side of the board, showing the plurality of twisted leads.

FIG. 4 is a composite view of FIGS. 3 and 4.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows an end portion of a printed circuit board (PCB) 10 arranged to serve as a test board for representative patterns of twisted lead pairs according to the invention. Those representative patterns are arranged in consecutive rows of through holes (shown from left to right) in a representative plurality of columns, only two of which are shown. More specifically, the PCB 10 includes rows 12 to 43, which for test purposes are substantially alike when positioned adjacent one another in the columns 44, 45. Because of the like nature of adjacent columns, only two are shown. PCB ResourcesPCB Resources

Sunstone is proud to offer complimentary PCB services with outside partners circuit board resources through our Sunstone ECOsystem for our customers. Not familiar with our Sunstone ECOsystem. Learn how Sunstone Circuits is working to help improve the circuit board industry.

The Sunstone ECOsystem is our strategic vision to consolidate and improve the PCB prototyping process for designers from concept-to-delivery through the integration of four discrete segments of PCB prototyping: knowledge, tools, libraries & parts, and fabrication.

Choose from one of the following areas of the Sunstone ECOsystem:

PCB (design) tools

Knowledge (& Partners)

Parts & Libraries

Manufacturing (Solutions Process Tracks Circuit Board Warpage To Improve Quality
Printed circuit boards (PCBs) power everything from portable radios to refrigerator-sized supercomputers, but they remain vulnerable to a simple, heat-induced threat: warpage. A warped PCB may cause a device to stop working. Boards that warp during manufacturing after expensive components are added can mean thousands of dollars in losses.

Now manufacturers have a new weapon against warpage: Thermoir¨Œ., a novel experimental technique developed at the Georgia Institute of Technology and licensed by Electronic Packaging Services (EPS) Ltd., Co. The patented process provides real-time data about PCB warpage, helping manufacturers avoid design problems and save money, said Thermoir¨Œ. developer Dr. Charles Ume.

"Electronic packaging companies can use the warpage information to make changes in their PCB design early," said Ume, an associate professor in the School of Mechanical Engineering. "That way, there's no mass production of a product that has a problem."

The heat that can warp PCBs is generated each time we turn on computers, camcorders or other PCB-run devices. Also, temperatures up to 230 degrees Celsius are an integral part of PCB processing.

"In addition, if the PCB is small, thin and also densely populated with components, as is the current industry trend, that is an invitation for warpage-related reliability problems," Ume said.

Noted EPS manager Dirk Zwemer: "It's not uncommon to see losses of one to three percent in a mature product, and it can be much higher for some designs."

Research sponsors, who were brought together through Georgia Tech's Manufacturing Research Center (MARC), include Motorola, MICOM, Ford Electronics, IBM, DEC and AT&T.

For this new process, Ume developed a special oven with a glass grating top, through which the PCB placed inside is visible. A white light shines through the glass grating onto the PCB, and an inexpensive, compact, charge-coupled device camera captures warpage digitally as it occurs.

The flat glass grating is etched with equally spaced parallel lines. It is placed above and parallel to the PCB. A beam of white light is directed onto the glass at a specific angle, causing the etched lines to create a shadow on the surface of the PCB. When the surface of the PCB curves due to warpage, a moir¨Œ pattern is produced by the geometric interference between the etched lines on the glass and the shadow of those lines on the PCB's surface. The more the PCB warps, the greater number of moir¨Œ fringes that appear.

Ume counts the number of fringes, puts them into an equation, and a computer determines how much warpage has occurred. The warpage process is displayed in real time on a television screen and recorded on video and on computer.

Developed in MARC's Advanced Electronic Packaging Lab, the Thermoir¨Œ. technique can be used to simulate the three major kinds of soldering processes -- infrared reflow, convective reflow and wave.

The automated oven system can reproduce any given soldering temperature history used in producing a board, while measuring PCB warpage at any specified time interval or temperature. That means the system can pinpoint which processes or designs may cause the most warping.

Companies can use the results to make design or process changes before production, such as changing soldering temperature profiles, reducing or extending processing times, relocating key components, and changing the types of materials used in the construction of the PCB.

The ability to measure thermally induced warpage also enables manufacturers to validate their numerical warpage predictions, which are created using finite element modeling techniques.If a certain amount of warpage is allowable, the new technique lets manufacturers measure initial warpage, rather than assuming the board is flat before transistors and other items are added. Manufacturers can then determine how much additional warpage develops during further processing or attachment of components.

Ume's technique also allows warpage measurement of the different materials that are sandwiched together to make a wiring board -- FR-4 laminates, fiber (prepreg), several varieties of copper foil and newly developed materials.

"These are unique measurement techniques, and the electronic packaging industry is very excited about them," Ume said. "Savings in scrap PCBs, rework, down time and loss in market share can run into the millions of dollars."

The research sponsors asked Ume to commercialize Thermoir¨Œ.. With help from Georgia Tech's Advanced Technology Development Center, the EPS Ltd., Co. licensed the technology and began offering help to the electronics industry in August 1994. Georgia Tech is a partner in the company.

Although EPS was formed to help the electronics industry, future Thermoir¨Œ. users could include manufacturers of foil, tape, resin, glass fibers and aviation equipment, said manager Dirk Zwemer. Other possibilities include putting Thermoir¨Œ. on an assembly line and making it more automated for the average worker.

"The technical applications are larger than the original sponsors knew it would be when they started," he said. "We want to be a good example of technology transfer."XJIO Board
The XJIO board is an expansion unit that enables you to improve the test coverage for a Unit Under Test (UUT) by verifying the signals right through to the external connections. It will integrate with your XJTAG test system to provide access to otherwise inaccessible areas of your circuit.

With a range of digital and analogue I/O pins on the board, you can improve fault isolation, verify power rail levels, and dispense with costly custom test jigs - even for non-JTAG boards.

Get the XJIO datasheet

Digital I/O
With 208 bidirectional digital I/Os, the XJIO board has been developed for maximum connectivity. The I/Os are all 5V tolerant. The default logic level is 3.3V, or you can re-configure the I/Os, in blocks of 16, to use any user-generated voltage between 3.3V and 1.8V.

Expandable
If more I/Os are required, the XJIO boards can be daisy-chained together via the reconfigurable external JTAG connector to reach the required density. All the connectors on the XJIO board are standard IDC, for economical and efficient cable assemblies.

Power Supplies
You can power the XJIO board from USB, for quick and portable test setup. Alternatively, if you need more than 80mA of current, there is a connector for a standard 12V power supply.

User Interaction
The switches and LEDs enable additional test control, allowing you to develop a complete and repeatable test solution.

Software
You can use the XJIO board with the whole XJTAG product range.