Advanced PCB design and layout for EMC Part 6
The aim of these crude guides is to ensure that the first reflection due to a mismatched trace occurs during the rise (or fall) time of the signal, where it will (hopefully) be masked by the rising edge and cause no problems for the receiver. If the trace was so long that its first reflection occurred after a logic transition had finished, the result could easily be double clocking or other digital glitches, so it becomes necessary to use matched transmission line techniques. Significant overshoot and ringing could still occur and so these guides might not be good enough for SI for some devices, and they do not control EMC as well as is often required for greatest cost-effectiveness in product design. Always read all the application notes for a device carefully to see if it has more stringent requirements than the above guides.
If the length of a trace is lt and the velocity of propagation along the trace is V, then that traces tp is given by: tp = lt /V. So we can modify the above guidance to say that: for SI, transmission line techniques are necessary when lt V.tr /2 or less.
For example, a stripline in an FR4 PCB with k = 4.2 has a bare-board V of 6.8ps/mm (see a later section), so a digital signal with a rise/fall time of 2ns (actual values, not data sheet specifications, see later) would need to use matched transmission lines for any traces that are longer than 147mm, for acceptable SI (98mm for the more careful approach).
We all like to use simple arithmetic to save time, but it is important to be aware that the above guides really are very crude indeed. Their assumptions about logic thresholds, eye patterns and EMC may not be true for other types of devices. And they take no account of the effects on V and Z0 of the capacitive loading of vias and devices (see later) or of the return path inductance caused by via holes or imperfect planes (also see later).
Engineers who take account of these complicating issues can achieve good designs in less time than those that merely follow the crude guides above. In fact, for good SI, a final design might require the use of transmission line techniques when tp exceeds a value that lies between tr/3 and tr/10.
Figure 6Fi) shows these various guides on a graph of rise/fall time against trace length.

From Figure 6C we can see that when a plain trace on a bare FR4 PCB has a length of about one-fortieth of the wavelength at the highest frequency of concern, it has an accidental antenna efficiency of about ¨ C20dB. To prevent traces becoming more efficient antennas than this, the equivalent of the crude tp tr /2 guide is that we should use tp tr /8 to determine how long a trace can be before we need to use matched transmission line techniques for good EMC. In frequency terms (see a later section) we can write this instead as tp 1/8f, where f is the highest frequency of concern.
Of course, using transmission line techniques for even shorter traces should improve EMC even more. The EMC equivalent of the more careful approach is to use transmission line techniques when tp exceeds tr /12. Continuing the example used above for SI, for good EMC a matched transmission line should be used where the trace length exceeds 37mm (or 25mm when using the more careful approach).
But the above EMC guides are based on crude assumptions, and it may even be that good EMC requires the use of matched transmission lines when tp exceeds a value that lies between tr /12 and tr /40.
Figure 6Fii) shows these various guides on a graph of rise/fall time against trace length.

To avoid the uncertainties in the above guides, simulation techniques are recommended. For good SI these should simulate the final design (the full details of the final PCB layout, plus all of its device loads) for all traces for which the bare-board tp tr/10, or tp 1/10 f.
For good EMC the final design should be simulated ¨ C at least for all traces carrying aggressive or sensitive signals (see later) ¨ C for which the bare-board tp tr/40, or tp 1/40 f (f being the highest frequency of concern).
Simulation is becoming increasingly affordable ¨ C and increasingly necessary in modern PCB layouts (a section on simulation is included later in this article). Where simulation is not an option, but good line matching is nevertheless required, the references given later provide some simple formulas that allow the effects of vias, stubs, load capacitance and imperfect return current paths to be taken into account. These calculations are not as accurate as simulation, so add an engineering margin of at least 25% to their results.
1.7 Increasing importance of matched transmission lines for modern products
Some modern high-speed interconnections can launch two or more data bits before the first edge of the first bit has even reached the end of the trace. Reflections at impedance discontinuities along the trace and at mismatches at its ends cause data-pattern-related noise on the line ¨ C as well as overshoot and ringing on rising and falling edges. The increasingly short real rise/fall times of modern sub-micron ICs are less tolerant of PCB layout, as Figure 6E shows.
So it is becoming more important to more accurately match and maintain Z0 along the whole length of a transmission line. Even via holes are becoming significant. Microwave design techniques (e.g. adding stubs of certain lengths) are increasingly needed to maintain Z0 within close tolerances for every millimetre along a trace.
1.8 It is the real rise/fall times that matter
When designing a PCB, the focus is naturally on the traces carrying signals with high edge-rates or the high frequencies, but even signals with a low frequency can cause excessive emissions. For example, a 1kHz clock generator with extremely short rise and fall times has caused emissions test failure all the way up to 1GHz; and a pulse-width-modulated (PWM) drive for a brushless DC motor has interfered with 6GHz radio communications, despite the switching rate being just a few tens of kHz.
Data sheet rise/fall time specifications (where they exist at all) are almost always just the maximum for the temperature range concerned ¨ C but actual rise/fall times are (almost) always shorter than data sheet specs, often a half or a quarter of the specified maximum.
In addition, older devices may have gone through a die-shrink or two, to put them on smaller silicon processes that make more money for their manufacturers ¨ C if so, their rise/fall times will be very much less than their data sheet specifications. Examples include HCMOS and F series TTL glue logic devices, the data sheets for which still quote the same rise/fall times as they did in 1985. But the actual silicon features used in current distributor stock of these IC types could now be ten times smaller than in 1985, and their rise/fall times could be at least ten times shorter than the maximum figures in their data sheets. HCMOS ICs are specified as having rise and fall times no longer than 5ns ¨ C but experience at the time of writing shows they can cause significant emissions at up to 900MHz, implying that their real rise/fall times might be as low as 300ps.
Another issue, mentioned briefly above and covered in more depth later, is that the capacitive loading of a trace, for example by connecting a number of devices along its length, reduces V even further. So it could very easily be the case that a well-established type of IC with data sheet rise/fall times of 2ns (e.g. F series TTL) ¨ C driving a multidrop bus ¨ C may need to use matched transmission lines for SI when trace length exceeds 20mm.
It is vital to know the actual rise/fall times of the digital signals that will be used in a PCB. It is impossible to do transmission line design using data sheet specifications for the vast majority of ICs. But few manufacturers even seem to know the rise/fall times of the devices they are currently manufacturing (and they care even less). To try to encourage manufacturers to supply this essential design data, we should all make sure we always ask for real rise/falltime data, including their maximum and minimum values (see WIZLOGIX PTE LTD

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In business since 2002, litevo has established itself as a premier provider of complete printed circuit solutions. By handling your PCB design, layout, fabrication, assembly, procurement, and related ancillary services all under one roof, litevo provides you with a unique, efficient, one-stop solution for all of your printed circuit board (PCB) needs.

litevo is a premier provider for all PCB Design Services, PCB Fabrication, and PCB Assembly Services. Our customers rely on us to handle all the features of their printed circuit boards projects. Our treatment of their PCB design, layout, fabrication, assembly, & material management is driven by continuous market pressure to shorten time-to-market, enhance asset utilization, keep abreast with up-and-coming technologies, and master complex process technologies. litevo s capabilities and services allow our customers to focus on their main competencies like research & development and sales & marketing.

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From prototype through production and quick-turns through standard and scheduled deliveries, let our highly competent domestic assembly operation handle all of your PCB Assembly Services. litevo looks forward to serving you for any of your PCB needsFlomerics Releases FLO/PCB Version 4.1

http://cn.newmaker.com 2007-9-23

(6 September 2007) -- Flomerics has released Version 4.1 of its FLO/PCB thermal design software with new features including the ability to model potting compounds, probe temperature values interactively, provide user-defined temperature ranges and search component libraries. FLO/PCB makes it possible to perform board-level thermal simulation very early in the design process. This analysis can help highlight potential thermal issues and provide engineers with more flexibility in resolving them before hundreds of hours of engineering time is invested in unusable designs.

Version 4.1 of FLO/PCB includes a new SmartPart object used to represent epoxy type solid cured potting compounds. It can be placed over all or part of either side of the PCB. Multiple (non-overlapping) potting compound regions can be defined. Any material in the resins material library supplied with the software can also be used or the user can define the properties using the potting compound material property sheet.

The new version also provides the ability to move the cursor over a temperature plot in the results visualization mode and report the point temperature. The legend scaling options have also been improved so that the user can define minimum and maximum values for the upper and lower bounds of the scale. The minimum and maximum values can also be derived from the coldest and hottest objects in the simulation results. Home | Services | Request a Quote | Technology | About Us | Contact Us | Technical Resources

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[April 26, 2005] Hunter Technology Participates in ACTA/Xilinx Partenership: 4/26/05

The PICMG ATCA 3.0 Design Kit can be used as a development platform for PICMG 3.0 full-mesh line cards supporting system configurations of up to 16-cards and port rates up to 3.125 Gbps.

Availability- Americas and selected countries in Europe

The heart of the reference design is the Virtex-II Pro device with RocketIO?Multi-Gigabit Transceivers (MGT), serving as the interface to the full-mesh backplane. The full-mesh card also allows application flexibility by reserving an area of the board for a plug-in "personality module" (PM). You can use the PM to implement any application-specific line card and easily connect to the full-mesh card through the included headers. A picture of the circuit board included in the Design Kit is shown in Figure 1 below while a high-level block diagram of the board architecture is shown in Figure 2.
The kit includes the circuit board, a mesh fabric example design, test and example designs as well as a complete board support package and extensive user guide. Software, card cages, design services and even power supplies are also available from Avnet and third party Design Kit participants.

Figure 1: PICMG ATCA development board

PICMG ATCA Design Kit:

The PICMG ATCA Design Kit accelerates development and deployment of a broad-range of applications. It uses a standard footprint that leverages existing infrastructure while ensuring interoperability through compliance with the PICMG standard. The kit provides a 15 channel, one port full mesh fabric interface, supports port rates up to 3.125 Gbps and includes an area for customers to develop application-specific personality modules.
The kit uses a Virtex-II Pro FPGA based Mesh Fabric Reference Design that includes all PICMG 3.0 defined card and shelf management functionality. The management firmware executes on one of the Virtex-II Pro's PowerPC processors running an embedded Linux operating system.
The Mesh Fabric Reference Design is included with the purchase of the Design Kit and is a great starting point for application development.

Figure 2: PICMG ATCA Block Diagram

Mesh Fabric Reference Design:
The Mesh Fabric Reference Design from Xilinx is a fully functional FPGA design that enables cost-optimized and highly flexible serial mesh backplanes with Mesh Technology on Xilinx Solutions. The example design has been targeted for Virtex-II Pro FPGAs with all the baseline functions required for a mesh backplane fabric interface, including ingress and egress datapath blocks, serial link interface blocks utilizing RocketIO MGTs, and a management interface block for control plane access to internal control and status registers. For ease of connection to other IP, the design utilizes the standard Local Link interface.
PICMG 3.0 specifies card and shelf management functionalities that are also implemented in the reference design. Figure 3 shows a high-level block diagram of the PowerPC based control plane logic developed using Xilinx's Embedded Developer's Kit (EDK).
The Mesh Fabric Reference Design data plane functionality is included in the Mesh Switch IP, shown in Figure 4.
All documentation and design files for the Full Mesh Fabric Reference Design are included with the purchase of a Design Kit.

Figure 3: IBM PowerPC Control Plane Logic

MultiBERT Test Environment:
Included with the design kit is a complete test environment, called MultiBERT, that is used to exercise the design with a comprehensive suite of test features. MultiBERT runs on a host computer (not included) and uses the example design native on the ATCA board. MultiBERT is the primary 'bring up' environment to get your development started and to validate your design. The following is a list of some of the key MultiBERT features:

Up to 120 simultaneous full duplex serial connections, in a
16-slot full mesh chassis
Automatic slot identification and backplane modeling, with
provision for user-defined backplane models
Control of the following settings through the MultiBERT GUI,
running on Windows:
Eight different serial test data patterns
Two different settings of low speed clock reference
Use of Multi-Gigabit Transceiver serial and parallel loopback
Multi-Gigabit Transceiver transmit polarity
Control of the following settings through FPGA compile-
time configuration:
Multi-Gigabit Transceiver Transmit Pre-Emphasis
Multi-Gigabit Transceiver Transmit Differential Voltage
Multi-Gigabit Transceiver Reference Clock Source
Reporting of the following statistics through the MultiBERT GUI:
Aggregate data transferred and error count
Per-connection data rate and error rate

Figure 4: Mesh Fabric Design Block Diagram

Feature List:

Xilinx 2VP50 FPGA
Compact Flash programming card
PICMG compatible board form factor
128 MB DDR SDRAM
Expansion daughtercard
User interface and display
Included with the Design Kit:
Development board
Example test design
Extensive MultiBERT test environment
User's guide
Schematics
Bill of materials
Complete documentation on CD-ROM
Optional elements:
Power supply
Card cage
Board level and FPGA design services
Supporting Intellectual Property cores
Xilinx development software tools
Training on Virtex-II Pro and designing with Multi-Gigabit Transceivers
Other related products and information:

Intel ATCA Boards and Chassis
Intel has a set of complimentary products that can be used to augment your Avnet/Xilinx ATCA board. These include a single board computer a 14U Chassis and a Chassis Management Module. Included with these boards are BIOS and Firmware to help speed your development cycle. For current information on Intel boards and chassis you can order from Avnet visit this url. http://www.intel.com/design/network/products/cbp/atca/index.htm

Xilinx Intellectual Property Cores
Xilinx has a variety of Intellectual Property (IP) Cores that are compatible with the Avnet/Xilinx ATCA Development Platform. Current IP Cores include support for: 1G & 10G Ethernet, Aurora, PCI Express, XAUI, RapidIO & Serial Rapid IO, Advanced Switching, SPI-4.2, Fibre Channel, SONET/SDH, CSIX, XGMII, HyperTransport, and PCI/PCI-X. Visit this url and search for the IP Cores you need in your system and then order them from Avnet.
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Intellectual+Property

Xilinx ATCA Web Portal
Xilinx has a comprehensive ATCA site that is a good starting point for learning all things ATCA. Visit this url to get started.
http://www.xilinx.com/esp/wired/optical/xlnx_net/atca_dev.htm

Avnet Authored ATCA Article in Xilinx Xcell Journal
Visit this web page to read over the Xcell Journal article on the Avnet/Xilinx ATCA

Version 4.1 also includes an advanced search capability for the component library. Users typically save components that they create into a library, from which they can be recalled and quickly placed into a new board design.
FLO/PCB Version 4.1 has also been updated to maintain bi-directional connectivity with Version 7.1 of Flotherm, Flomerics?system-level thermal modeling tool. For example, the same PCB design that is used to create a FLO/PCB model can also be incorporated into a system-level model in Flotherm. This saves time for the mechanical engineer in updating the system level model, if necessary, while reducing the chance of errors caused by miscommunication. The results from the systems level analysis can also be exported directly to the board-level simulation, making it possible for the board designer to apply the air flow and temperatures from the system-level simulation to the board being designed. This approach keeps all team members in sync and enables them to contribute to concept development in real time. Founded in 2000, Ellington group is principally engaged in the manufacture and sale of high density double-sided and multi-layered printed circuit board. It has rapidly grown up as one of the largest PCB manufacturer in southern China.
With our strategically located production facilities at cost-competitive region, Zhongshan city of China, we have a skillful and experienced workforce of over 4,500 employees on a production floor area of over 1,500,000 square feet. Currently,our annual production capacity is over 18 million square feet and is planned to expand by more than 50% in coming year.Our customer base is well diversified including worldwide market leaders in different electronics sectors,such as computer and computer peripheral, telecommunication and networking,automotive,power supply and consumer electronics. We provide for our customers with wide arrays of PCB.Ellington is committed to upgrade our state-of-art manufacturing facilities with high-technology and process automation machineries, enabling us to keep abreast with advanced technologies and to improve efficiency effectively.
The management is determined to place strong emphases on quality control,cost control and on-time delivery. Ellington's mission is to be a leading PCB manufacturer which can meet with customer total satisfaction. Cycle Time is our Strength...
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Whatever PC based schematic input you provide, we have automated routines to convert your netlist to the desired format.

Design Considerations for Dallas Semiconductor Real-Time Clocks

Abstract: A real-time clock (RTC) allows a system to synchronize or time-stamp events to a time reference that can be easily understood by the user. Because RTCs are used in an increasing number of applications, designers should familiarize themselves with these RTCs to avoid design problems. This application note provides a basic overview of RTC operation, design issues, and troubleshooting techniques.

Selecting an Interface
Real-time clocks (RTCs) are available in a wide range of bus interfaces. Serial interfaces include I2;C, 3-wire, and Serial Peripheral Interface (SPI?). Parallel interfaces include mux-bus (multiplexed data and address bus) and designs with separate address and bytewide data inputs.

The choice of interface is often determined by the type of processor being used. Many processors include I2C or SPI interfaces. Others, such as 8051 processors and their derivatives, support multiplexed address and data buses. Timekeeping NV RAMs use the same control signals as SRAMs, to which many processors provide an easy interface, and include battery-backed RAM in various densities. Finally, phantom clocks "hide" behind battery-backed RAM and use a 64-bit software protocol to gain access to the clock. A phantom clock can therefore provide time and date infromation without using any memory space.
Battery Backup Function
In some applications such as VCRs, the time and date information will be lost if power is removed. Other applications require that the time and date remain valid even if the main power supply is off. To keep the clock oscillator running, a primary or secondary battery or a super capacitor may be used. In this case, the RTC must be able to switch between the two power supplies.

If a primary battery, such as a lithium coin cell, is used for backup, the RTC should be designed to draw as little power as possible when running from the battery. In this situation the RTC will switch its internal supply bus to the battery and go into a low-power mode. Communications between the microprocessor and the RTC are usually locked out (often called write protect) to keep the battery current at a minimum and to prevent data corruption. The VCC voltage level at which communications is locked out is usually defined in the data sheet as VTP (Trip Point Voltage).

Many clocks include an oscillator control bit, usually called the clock halt (CH) or enable oscillator (EOSC) bit. This bit is usually located in bit 7 of the seconds register, or in a control register. In almost all clocks with this bit, it is preferable that the oscillator be off when the battery is initially attached. This conserves the battery until the system is powered up. It also allows the system designer to set up a manufacturing flow so that no battery current is drawn after a fresh lithium battery is installed.. When the end user first powers the system, the firmware/software should start the oscillator and prompt the user for the time and date.

Most Dallas Semiconductor products that include a battery input pin include on-chip reverse charging protection circuitry. Regulatory agency data and Conditions of Acceptability information can be found at UL Recognition.

Lithium batteries are normally rated to operate from -40. Packages that include the battery and have exposed battery pins, such as the SmartSockets, should never be water washed. Water washing will short the battery terminals, and therefore draini the batteries.
Clock Modules, Freshness Seal and Shelf Life
The majority of the current consumed by a clock while in battery-backed mode is from the oscillator. All clock modules with embedded crystals and batteries are shipped from the factory with the oscillator disabled. While the oscillator is disabled, the battery current is less than the self-discharge of the battery, or about 0.5% per year at room temperature.

Some timekeeping NV RAM modules use a clock-controller IC and a SRAM. The oscillator is disabled and the SRAM is electrically disconnected from the battery when shipped from the factory. The battery will be connected to the SRAM after VCC is removed for the first time. This function is often called "freshness seal," and is used to conserve the battery until the module is first used. Other timekeeping NV RAM modules are monolithic (controller and SRAM in one IC) and require no freshness seal.
Module Packages
Timekeeping NV RAMs, mux-bus clocks, and some watchdog and phantom clocks are available in module and/or PowerCap packages. Modules include an embedded 32,768Hz crystal and a lithium battery, making PCB design easier. However, crystals and batteries cannot tolerate the temperatures encountered during the reflow process. Consequently, modules can be attached manually or inserted in a socket after reflow. Modules can also be attached to the PCB using wavesolder, as long as the lithium battery is not exposed to temperatures above +85.

PowerCap products use a two-piece construction to provide a device that can be surface-mounted using the reflow process. The module base, containing the RAM and clock, is mounted to the board using standard reflow techniques. The PowerCap top, containing the heat-sensitive battery and crystal, is snapped onto the base after soldering.
Clock Formats
There are three major data formats used in RTCs: binary-coded decimal (BCD), binary with separate registers for the month, date, year, etc., and elapsed-time counters.
BCD
The BCD format is the most common. One reason for its popularity is that the time and date can be easily displayed in a human-readable format with no "conversion." Each 8-bit register represents two digits (one nibble per digit). Each 4-bit nibble can hold the binary representation of the digits 0 through 9. An example of the register map for a typical BCD format clock is shown in Figure 1.

Since some of bits are not needed for a particular time or date field, those bits can be used for special functions, general-purpose read/write bits, or can be hardwired to read back as always one or zero, depending upon the design. In Figure 1, bit 7 of the seconds register is used for the clock halt (CH) bit. (See the DS1307 data sheet for an example.)

Figure 1. Typical time and date register map (BCD format).
Binary
The second clock format is the binary format (Figure 2), with separate registers like the BCD format. The binary format is normally a programmable option on some clocks with the BCD format. (See the DS12885 data sheet for an example of this format.)

Figure 2. Typical time and date register map (binary format).
Elapsed-Time Counter
The elapsed-time counter (ETC) uses a single, multibyte register representing the time in seconds from some reference point (zero epoch). A common value is 00:00:00 January 1, 1970 GMT. The binary value in the register then represents the elapsed time from that point. Software routines must be used to convert the 32-bit value to a readable time and date, and to convert user entries to a binary value. The C ctime() function converts the elapsed time, in seconds, to a date/time string.

Application note #511, Using the DS1672 Low-Voltage Serial Timekeeping IC, presents example routines for converting elapsed-time values to and from date strings. The DS1318 is a 44-bit ETC. The lower 12 bits provide sub-second resolution, to 244|?
e◤?
`s. The upper 32-bits increment once-per-second, as described above. See application note 2740, Accessing the DS1318 Clock Registers for an example application.

ETC clocks are useful when the clock is needed to measure the time between two events. Calculating the time elapsed between two events requires subtracting one value from another, while a BCD-formatted RTC would require more complex conversion routines.

For BCD-formatted RTCs, the time and date registers are typically updated once per second. The roll-over value for the date will vary depending upon the month, and for February, by year. The day register (except for multiplexed-bus clocks) is not tied to any other register, will increment at midnight, and will roll over from 7 to 1. The programmer can select any particular day as 1, as long as the assignment is consistent throughout the program. On multiplexed-bus clocks, however, Sunday must be 1 because the day register is used for the daylight saving test. The test for daylight saving is done at midnight on the preceding midnight roll-over, which must be accounted for when testing the daylight saving function.

When changing from 12-hour mode to 24-hour mode, or from BCD to binary or binary to BCD, the time, date, and alarm registers must be re-initialized.
Crystals and Accuracy
The crystal oscillator is one of the most accurate circuits available for providing a fixed frequency. A 32,768Hz crystal is used for most RTCs. By dividing down the output of the oscillator, a 1Hz reference can be used to update the time and date. The accuracy of the RTC is dependent mainly upon the accuracy of the crystal. Tuning-fork crystals have a parabolic frequency response across temperature (Figure 3). An error of 23ppm is about 1 minute per month. For further reference, see the Real-Time Clock Calculator. Crystals are tuned to oscillate at the correct frequency under a particular capacitive load. Using a crystal tuned for a 12.5pF load on an RTC designed to present a 6pF load to the crystal will cause the clock to run too fast.

Figure 3. Crystal accuracy vs.temperature.
Crystal Connections
All Dallas Semiconductor RTC oscillators have internal bias networks. The crystal should be connected directly to the X1 and X2 pins with no additional components (Figure 4). The crystal should also be as close as possible to the X1 and X2 pins, and a ground plane should be placed beneath the crystal, X1, and X2 (Figure 5). Digital signal lines should be routed away from the crystal and oscillator pins. Low-power crystal-oscillator circuits can be sensitive to nearby RFI, which can cause the clock to run fast. Consequently, components that radiate significant levels of RFI should be shielded and located away from the crystal.

Figure 4. RTC equivelent circuit showing the internal bias network.

Figure 5. Typical crystal layout.

PC boards containing tuning-fork crystals, such as those used with RTCs, should not be cleaned using ultrasonics. The crystal can be damaged by resonance vibration.
Oscillator Startup Time
Oscillator startup times are highly dependent on crystal characteristics and layout. High ESR and excessive capacitive loads are the major contributors to long startup times. A circuit using a crystal with the recommended characteristics and following the recommended layout will usually start within one second.
Checking for Oscillation
When checking for oscillator operation, a designer may initially considerconnecting an oscilloscope probe to the oscillator input (X1) or output (X2) pin. That approach is not recommended with a RTC. Since the oscillator is designed to run at low power (which extends operating time from a battery), loading the oscillator with an oscilloscope probe will usually stop the oscillator. If the oscillator does not stop, the additional loading will reduce the signal amplitude, and can cause erratic operation such as varying amplitude. Oscillation should, therefore, be verified indirectly.

Oscillation can be verified several ways. One method is to read the seconds register multiple times, looking for the data to increment. On RTCs with an OSF (Oscillator Stop Flag), clearing and then monitoring this bit will verify that the oscillator has started and is continuously running. These methods will not work if the designer is troubleshooting a design and cannot communicate with the RTC. An alternate method is to check the square-wave output on RTCs with a square-wave output. Check the data sheet to verify whether the RTC must be written first to enable the oscillator and square-wave output. If the square-wave output is open-drain, a pull-up resistor must be connected between the square-wave pin and a voltage supply for proper operation. The square-wave output can also be used to verify the accuracy of the RTC, although, a frequency counter with sufficient accuracy must be used for this.
Backup Supply Input
Most Dallas Semiconductor RTCs include a backup supply input pin, which keeps the RTC running while the main supply is off. Most RTCs are designed so that a lithium coin cell can be used to power the RTC while VCC is absent.

When VCC is below the minimum operating value (VTP), the RTC disables the communications interface. This serves two purposes: it prevents accidental writes to the RTC while VCC is dropping; it reduces the power needed by the RTC to maintain oscillator, time, and date operation. Disabling access to the part when VCC is below VTP is often called "write protect." While the RTC is operating from VCC, the VBAT input will be at a high impedance. If a battery is not connected to the VBAT input, or if it is connected with diodes in series (Figure 6), the VBAT input can float high. This, in turn, can cause the RTC to go into write protect. Reverse-charging protection is provided internally on most Dallas Semiconductor RTCs, which eliminates the need for external diodes. Check the following link for information about UL recognition of the reverse-charging protection.

Figure 6. Incorrect battery connection.

Figure 7. Correct battery connection.
Calculating Battery Life
When designing a system with an RTC, the backup power source must be selected based on the system requirements. If a system is expected to run from the main power source most of the time, the backup supply may only need to power the clock for a few hours. In other applications, the backup supply must power the clock for long periods of time.

For RTCs with a separate backup supply input (VBAT or VBACKUP), the battery backup time is calculated by dividing the battery capacity in Ampere-hours by the expected backup current. Here are two examples of how this capacity is calculated.

Example 1. A BR1225 Li+ battery has a rated capacity of 48mAH. While the DS1307 is powered by VBAT, the current drawn by the VBAT input is specified at 500nA maximum with the SQW/OUT off. Therefore, 0.048 / 500e-9 = 96,000 hours, or about 10.9 years. Note that this assumes that the battery has negligible self-discharge.

Example 2. A DS1337 is used in an application where a single battery supply powers the entire circuit. Active current (current while the I2C serial-interface is active) is rated at 150A per hour. This number would be added to the current drawn by the microcontroller, the I2C pullup resistors, and any other devices powered by the battery. The battery capacity would then be divided by the total current, as in Example 1, to obtain the expected battery life.

For applications that require a few hours or days of operation from the backup supply, a large capacitor or super capacitor could be used. RTCs with a built-in trickle charger support the charging of super capacitors. Refer to application note 3517, Estimating Super Capacitor Backup Time on Trickle-Charger Real-Time Clocks, and the on-line super capacitor calculator for more information.
Reading and Writing the Time and Date
Reading and writing the time and date registers is an asynchronous event, separate from the automatic update of the internal registers. Two types of read errors can occur when the time and date registers increment while being read. First, the data could change while a single register is being read, or, second, the data could change during the time between reading two registers. Assume, for example, that the clock increments from 11:59:59 to 12:00:00 during a read of the seconds, minutes, and hours registers. The time read could be 12:00:59, which is incorrect.

Some method must be used to prevent these read errors. Most Dallas Semiconductor Maxim clocks ensure that the time and date registers can be accessed without the values getting corrupted from an internal register update while the read or write is in progress.

A second set of registers (secondary buffer or "user" registers) are used on most serial clocks. When the time and date registers are accessed, the current time and date are transferred to the secondary registers. A burst read will take the data from the secondary registers, which remain unchanged while the internal registers continue to update. The next access (when CE goes active on a 3-wire device or a START on I2C interface devices occurs) will transfer the data again. When writing to the time and date registers, the internal countdown chain is reset when the seconds register is written. That allows the program almost one second in which to write the remaining time and date registers before a rollover occurs.

On timekeeping NV RAM clocks, either a transfer enable (TE) bit or (R)ead and (W)rite bits are used to "freeze" the user registers. Setting the R bit or the TE bit keeps the user registers from being updated from the main registers. Resetting the TE bit or the W bit after writing the user register loads the internal time and date registers with the values from the user registers.

The block diagram in Figure 8 shows typical functions for transferring time and date information between the internal registers and the user interface. The 32,768Hz signal from the oscillator is divided down to 1Hz by a countdown chain that has a reset input. The 1Hz signal from the countdown chain drives the BCD seconds counter/register. The ripple output from the seconds counter feeds the minutes counter/register, and so on. Changing the R and W bits in the control register synchronizes the transfer of data from the internal registers to the user registers. The Transfer Control block sends a reset to the countdown chain when transferring data from the user registers to the internal registers. This allows synchronization of the clock to an external reference to within approximately 244|?
e◤?
`s (most clocks do not reset the first three dividers, to the 4,096Hz signal; 1/4,096Hz244|?
e◤?
`s). Most serial-interface clocks reset the countdown chain whenever the seconds register is written.

Figure 8. Block diagram showing internal and user copy of time and date registers.

On mux-bus clocks, several methods are available to ensure that the time and date registers do not change while being accessed. The following methods are available:

SET Bit
When the SET bit in register B is set to a one, the user copy of the double-buffered time and date registers is latched. The internal registers continue to update normally.

UIP Flag
The Update In Progress (UIP) flag will pulse once per second. After the UIP bit goes high, the update transfer occurs 244|?
e◤?
`s later. If a low is read on the UIP bit, the user has at least 244|?
e◤?
`s to read the time and date and avoid errors due to an update.

UF Interrupt
If enabled, an interrupt occurs after every update cycle, thereby indicating that over 999ms are available to read valid time and date information.

Default Register Values
Unless otherwise noted in the data sheet, the initial power-up register values are undefined. That is, they should be treated the same as DRAM or SRAMs; on initial powerup, the data will, for practical purposes, be random.
Troubleshooting New Designs
The following sections discuss some RTC problems and how to troubleshoot them.

Cannot Communicate with the RTC
When trouble-shooting a new design, there are several methods to help identify the cause of this problem. If the RTC appears not to respond at all, try to determine if it will not read, write, or both. If the part has a software-enabled feature such as a square-wave output, try to enable that feature to determine if you can write to the part. On I2C serial devices, an oscilloscope can be used to verify if the clock is sending an acknowledgement at the end of each byte.

The following paragraphs describe some additional trouble-shooting hints for communicating with the RTC.

Battery-backed RTCs use a comparator to switch between VCC and VBAT. Some RTCs use the battery voltage as the reference, while others use a bandgap voltage reference to determine when VCC is valid. Once VCC drops below the comparator trip point, read and write access is not possible. Preventing access below a certain voltage helps to prevent inadvertent writes from a processor that no longer has a valid supply. Also, When VCC is above the trip point, the comparator switches the internal circuits to VCC, thereby preventing battery drain. A floating battery input, an input with a diode between the battery and VBAT, or a battery with too high a voltage can prevent communications with the RTC. Make sure that VBAT is at a valid level and that there are no diodes between the battery and the battery input pin.

To determine whether the power-fail function is causing problems reading and writing the RTC, it is often useful to observe a function that only operates when the RTC is out of power-fail (i.e., operating on VCC). Some RTCs have a RST or PFO output that can be observed. Since these outputs are often open-drain, a pull-up resistor may be needed. On other devices, such as the DS12887 and other multiplexed-bus parts, the square-wave output only operates when the part is operating on VCC. On some devices, including many seria-interface RTCs, the square-wave output is open-drain, and a pull-up resistor must be in place to observe the signal. Consequently, check the RTC's data sheet to determine if it has a square-wave output signalt. If read/write access is intermittent, use an oscilloscope to see if the output is also intermittent.

Serial clocks require that the "command byte" or "slave address" be written to the device correctly. An incorrect command/address often causes the device to ignore read routines. In those cases, the data I/O pin stays in a high-impedance state. On a serial bus with pull-up resistors, the data read back will usually be 0xff. On 3-wire interfaces, if the I/O pin has an internal pull-down resistor, the data will often be 0. In other cases, the data read back will often be whatever was the last bit of the command byte.Some serial clocks use a separate supply input for the outputs, to allow interfacing to processors running at a lower supply voltage. Failure to connect a valid supply to the input will keep the I/O pin from driving high. Finally, data out may be all ones or zeros if the software does not switch the microprocessor's port pin that is connected to the clock's I/O pin from an output (while writing the command byte) to an input (for reading data from the clock).

Invalid Time and Date Values
Most time and date registers can accept any value, including invalid ones. If an invalid value is entered into a register, the value will increment until the bits used for rollover comparison match, or until the counter reaches its maximum count. If the seconds register is written to an invalid value such as 60, in most cases the RTC would increment the invalid value until it reaches 69, at which point the seconds register would roll over to 40 seconds. Invalid values can also be caused if the clock is in the wrong mode, e.g., binary instead of BCD, or 12 hour instead of 24.

If the registers appear to be counting from valid values to invalid values, the cause is usually a software routine that converts BCD values to or from ACSII or binary values incorrectly. The software routines should be checked for proper conversion of all possible values, since errors usually only affect some values. by An oscilloscope will also verify that the RTC is counting correctly and generating correct data.

Data Loss/Data Corruption
Data loss is usually caused by one of two things: inadvertent writes to the clock, or negative voltage glitches being applied to the IC. Data loss caused by negative voltage inputs to the IC can sometimes be identified because the CH or EOSC bit (on clocks with an oscillator control bit) will be in their default "halt" state. For clocks with an oscillator stop flag (OSF) bit, the OSF bit will usually be set. Additionally, the data in most, if not all, of the registers will be corrupted. Inadvertent writes normally occur during power cycling as well, but will usually only affect one register. It usually does not affect serial clocks.

Some switching power supplies will, on power-up and/or power-down, create a voltage spike on VCC. This voltage spike can go negative by 5V or 6V, or more. This negative voltage will couple onto the internal supply of the clock through input-protection diodes. If the power supply can source more current than the battery, data will be lost. In most cases, a Schottky diode can be used to clamp the negative voltage spike.

Another source of negative voltages on the clock can come from RS-232 connections. If the PCB with the clock IC is powered down, and a powered PC or other instrument is connected to that board with an RS-232 connection, the RS-232 transceiver can pass the negative marking voltage onto other ICs on the unpowered board (see Figure 9). To verify that this as a problem, try cycling power on the system with the RS-232 link disconnected.

Figure 9. System connected to a PC using RS-232.

Data also corrupt when VCC falls too fast, which can either cause all the time, date, and RAM data, or only one or two bytes of data to corrupt. This second issue (one or two bytes of corrupted data) normally affects parallel-interface RTCs, e.g., timekeeping RAMs, but can also affect multiplexed-bus RTCs, as explained below.

The power-fail circuitry on battery-backed RTCs usually includes some filtering to ensure that a momentary glitch on VCC does not cause an inadvertent write protect. The write can occur if VCC falls too fast. As VCC falls, the output voltage-high level from the microprocessor's CE, OE, and WE outputs (or other control signals) usually tracks VCC. Therefore, the RTC's CE, OE, and WE inputs also follow VCC. As with typical static RAMs, if CE, OE, and WE are all low, the RTC is in a write cycle. If the RTC does not enter power-fail before VCC reaches the input thresholds of the control inputs, the RTC's internal logic will cause a write to occur.

In the case of multiplexed-bus clocks, the address information is latched on the falling edge of ALE. If R/W and CS go low before the part is in write protect, the data in the last register accessed will be corrupted. One should verify that the VCC rise and fall times meet the data sheet requirements. If the seconds register is corrupted, the RTC may appear to lose time in battery backup. The seconds register can be written to zero when corrupted. Consequently, when VCC is again applied, the resulting time will be slow by however many seconds the register was at when VCC was removed.

If all the data is corrupted, then VCC fell too fast for the RTC to switch over to the backup supply and maintain the time and date information. This problem can affect both serial-interface and parallel-interface RTCs.

Intermittent Data Loss
Intermittent data problems have been caused by interrupts routines that are not handled correctly. In some cases, the time and date information is copied to RAM, and the copies are not kept in sync. Additionally, in-circuit emulator (ICE) hardware can be configured improperly, causing erratic behavior.

Oscillator Problems
The most common reason for the clock not to increment is that the oscillator has not been enabled. Most Dallas Semiconductor clocks have a bit, usually located in the seconds register, that must be set before the oscillator will run.

The oscillator circuit is designed to be low power to prolong battery life. Problems with the crystal connection can reduce the loop gain, preventing the oscillator from running. External capacitors or other components connected to the crystal will also reduce the loop gain, increase the startup time, or prevent oscillation. Crystals with an ESR above the recommended maximum value will also decrease the loop gain. Some water-wash solder fluxes can appear to leave the PCB clean, while leaving enough contaminates to prevent oscillation. See application note 58, Crystal Considerations for Dallas Real-Time Clocks for more information. Mentor Graphics HyperLynx 7.7 Introduces Ground-Breaking SERDES Technology and Major Productivity Enhancements

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