Author: Mr. Flemming Boisen
Company: Texas Instruments
Abstract:
The reduction in pitch size increases the micro-via-layer count for HDI PCBs. By optimizing the design, significant layer reduction can be achieved. However, the PCB technology becomes more demanding. PCB fabricators are not always willing to follow the miniaturization route but advanced electronic components need the advanced design for best functionality of the electronic devices and last but not least the lowest cost.

Requirements:

- 3+ years of working experience in accounting or finance
- Experience in a foreign owned company is preferred
- Knowledge of the full set accounts closing, taxation, import and export rules is required
- Knowledge of SAP FI/CO, and A/R is preferred
- Able to work independently and work with external and internal auditors.
- Positive and hands-on approach with a keen attention to details
- Good command of both written and spoken English
- Good analytical skills, systematic and well-organized.
- Bachelor Degree in finance or accounting; CPA is preferred

Engineering Manager (5220)

Job Description:

- Manage an off-shore software development team within the 7100 EMS development organization.
- Group responsibilities include software implementation of 7100 EMS applications and features, including North Bound Interfaces and tools to support EMS scalability testing, such as network element simulators.
- Specific duties include staff management, project planning, project status reporting and project-related vendor management.

Requirements:
- Excellent organizational, project management
- Verbal and written communication skills, including proficiency in English.
- A minimum of 5 years experience in project management and/or technical management.
- 5 years of experience in a product development of transport products, preferably in the development of management systems and/or management interfaces.
- Additionally familiarity with Microsoft Project, MS Word, and MS PowerPoint.
- BSEE/BSCS or equivalent experience required.

Senior Hardware Engineer (CPE)

Job Description:
- Work as a senior team member on developing application hardware for Tellabs broadband access product.
- Activities are self-determined and involve the assessment and resolution of complex problems at the project/functional level.
- Lead a project, make decisions, solve complex issues, analyze the requirements, breakdown to high level designs, write detailed design documentation and develop schematics with OrCad, Cadence, or similar CAD software.
- Design PCB circuit board utilizing Microprocessors, Network Processors, FPGA/CPLD, Memory, Framers and Line Interface ICs.

Requirements:
- A Minimum of 4 years telecommunications hardware product development experience; full cycle development experience
- Good verbal, interpersonal, and technical leadership skills.
- Must have background in carrier class voice and broadband access products involving DSL, PON, ATM, Ethernet or IP.
- Proficiency in digital and analog circuit design for broadband and narrow band communication application is required.
- Design experience with customer premise equipment such as PON ONT , xDSL Modem, Cable Modem, HomeGateway or Set Top Box is preferred.
- Extensive vendor relationship and design for cost reduction experience for large volume product manufacture are desirable.
- Knowledge of appropriate design, manufacturing, and reliability considerations for customer premise equipment.
- BS or MS degree in Electrical Engineering or Computer Engineering

Senior Testing Engineer

Job Description:
- Will work closely with a skilled team of development engineers to design & execute feature testing and documenting test results for broadband access product.
- Activities are self-determined and involve the assessment and resolution of complex problems at the project/functional level.
- Set up a testing platform for telecommunication broadband product development.
- Design and execute feature testing via scripts or automation testbed, and documenting test results.

Requirements:
- A minimum of 4 years telecommunications product testing experience.
- Good verbal, interpersonal, and technical leadership skills.
- Must have strong trouble shooting skills of testing WAN/LAN equipment with network traffic analyzers and hardware interface testers.
- Hands-on experience of feature verification or system integration testing of carrier class voice and broadband access products such as DSL, PON, ATM, Ethernet or IP is required.
- Experience on Tcl/Tk, Ksh or Perl script is desirable.
- Experience on setting up test bed from scratch for Switches/Routers, Video, IPTV or optical transport is a plus.
- BS or MS degree in Electrical Engineering or Computer Engineering

Program Manager

Job Description:
- Work as a team member on managing Tellabs broadband access product development.
- Assist executive team to manage various product development stages including prototyping and testing to effectively meet milestones.
- Monitor progress and help executive team to assure that work performed follows generally stated objectives and is completed on time and within budget.
- Make appropriate adjustments to maintain project goals, when necessary.
- Manages team development and maintains administration responsibilities including action items follow up and generating progress report.
- Adhere to all corporate policies and budget constraints. Interface with program management team in USA.

Requirements:
- A minimum of 4 years telecommunications project or program management
- Good verbal, interpersonal, and technical leadership skills.
- Be able to handle multiple projects and priorities at any given time and interface within various department in the local company as well as with the headquarter in USA.
- Quality control experience such as CMMI or 6-sigma program is desirable.
- Previous experience as a product developer is a plus.
- BS or MS degree in Engineering or Business Administration hardware manuals.
Performs complex board level unit and integration test. Debugs complex problems at the system level. Provide guidance and leadership to test team members of Hardware DVT, Mechanical DVT, System Test, and Regulatory Compliance.
Writes complete unit and integration test plans.
Mentors more junior engineers in the completion of complex tasks. Participates in defining the design and implementation processes and procedures. Participates in Cisco s patent program.

REQUIRED KNOWLEDGE, SKILLS & EXPERTISE

Expertise developing printed circuit boards for digital systems.
Skill using schematic capture tools like Mentor Graphics ePD/DxDesigner (Viewdraw).
Expertise using Networking silicon: PHYs, MACs, and Network Processors.
Skill utilizing FPGAs, Verilog or VHDL language, simulations, timing analysis, and back-end compilation.
Expertise with high speed SerDes design, PLL design and LVDS, LVPECL, CML and other high-performance I/O technologies.
Familiarity with board level simulations for signal integrity, power integrity, and timing analysis. Expertise correlating simulation results with lab measurements using oscilloscopes, TDRs and spectrum analyzers.
Knowledge of power systems, power supplies, and DC-to-DC regulation concepts and components.
Expertise designing to and testing for regulatory compliance: Safety, EMC, and Environmental. Expert knowledge of PCB technology.
Skill resolving problems at the system level. Expert knowledge of networking principles, theories and commonly used concepts.
Skill in the application of old and new networking technology into complex designs.
Basic knowledge of ISO9001 and it's implications on development environment.
Some knowledge or skill writing or maintaining diagnostics firmware.
Desirable skill planning projects with a good understanding of product life-cycle methodology.
Desirable skill in protecting intellectual property through patents.
Desirable expertise partnering with marketing, customer engineering, or sales and incorporating customer inputs into product direction and priorities.
Desirable skill presenting confidently in front of a large group.

DESCRIPTION OF THE JOB APPLICANT
Understands the product level and related product level architecture (for example: competitive products). Works under department strategy and direction. Translates department goals into own work assignments and prioritizes accordingly. Independently determines and develops approach to solutions. Work is reviewed upon completion for adequacy in meeting objectives. Sponsors and models exemplary team interaction. Shares information and communicates clearly to team members and cross-functional teams. Encourages and accepts performance feedback. Problem solving requires creativity and ingenuity using knowledge gained from experience. Exercises broad judgment. Promotes cooperation between team members and resolves conflicts. Demonstrate Leadership. Acknowledged technical expert on products developed. Innovation and Learning. Dedication to Customer Success.

REQUIRED EDUCATION AND JOB EXPERIENCE
BSEE combined with 5+ yrs related experience, or an MSEE combined with 4+ years of related experience. Recent direct experience developing numerous printed circuit boards, including participation in each of these activities: concept and architecture, circuit design, component selection, schematic capture, timing and power analysis, CAD layout, fabrication, debug, testing, and release to production.

KEYWORDS
Networking, Hardware, Board Design, Digital Design, Circuit Design, Schematic Capture, System Engineer, Design, Project Leader, PCB; Printed Circuit Board, Timing Analysis, Signal Integrity, Board Simulation, Regulatory Compliance, EMC, Viewdraw

DSBU: HW Engineer II (System Engineer with 2-5 years experience)

JOB DESCRIPTION AND RESPONSIBILITIES
Participates on a project team of engineers responsible for the specification, design, development, test, enhancement, and sustaining of networking hardware. Contributes to board level architecture design and writes functional specs. Develops complex circuit designs for multiple modules (with supervision). Partners with CAD and Manufacturing Engineers in developing new boards. Work under direction from a project leaders but also interface with team members of ASIC, System Software, Diagnostic Software, and Mechanical Engineering. Writes major portions of design specifications and hardware manuals. Performs complex board level unit and integration test. Debugs problems at the board level. Interfaces with test team members of Hardware DVT, Mechanical DVT, System Test, and Regulatory Compliance. Writes major portions of unit and integration test plans. Follows standard design and implementation processes and procedures. bbs.chinahrlab.com

REQUIRED KNOWLEDGE, SKILLS & EXPERTISE
Skill developing printed circuit boards for digital systems. Skill using schematic capture tools like Mentor Graphics ePD/DxDesigner (Viewdraw). Expertise resolving problems at the module or multiple module level, based on knowledge of debugging and testing concepts. Knowledge of PCB technology. Basic skill with circuit board debug and test equipment. Working knowledge of Internet and networking products and technologies. Limited skill in the application of basic networking theories and concepts.
Basic understanding of ISO9001 and it's implications on development environment. Desirable knowledge of Networking silicon: PHYs, MACs, and Network Processors. Desirable expertise with FPGAs, Verilog or VHDL language, simulations, timing analysis, and back-end compilation. Familiarity with high speed SerDes design, PLL design and LVDS, LVPECL, CML and other high-performance I/O technologies. Desirable skill performing board level simulations for signal integrity, power integrity, and timing analysis. Desirable skill correlating simulation results with lab measurements using oscilloscopes, TDRs and spectrum analyzers. Familiarity with power systems, power supplies, and DC-to-DC regulation concepts and components. Desirable knowledge designing to and testing for regulatory compliance: Safety, EMC, and Environmental. Some knowledge or skill writing or maintaining diagnostics firmware. www.chinahrlab.com

DESCRIPTION OF THE JOB APPLICANT
Understands product level architecture. Ability to develop complex designs. Ability to multitask. Works under general supervision. Follows established procedures. Work is reviewed for soundness of technical judgment and overall adequacy and accuracy. Teamwork. Excellent written and verbal communications, team and people skills. Shares information and communicates clearly to team members. Encourages and accepts personal feedback. Uses acquired professional knowledge to work out problems and make sound technical decisions. Exercises judgment within defined standards and consults with management. Promotes cooperation between team members. Innovation and Learning. Dedication to Customer Success.

REQUIRED EDUCATION AND JOB EXPERIENCE
BSEE combined with 2-5 yrs related experience, or an MSEE combined with 1-4 years of related experience. Recent direct experience developing a printed circuit board, including the involvement in each of these activities: concept and architecture, circuit design, component selection, schematic capture, timing and power analysis, CAD layout, fabrication, debug, testing, and release to production.

KEYWORDS
Networking, Hardware, Board Design, Digital Design, Circuit Design, Schematic Capture, System Engineer, Design, PCB; Printed Circuit Board, Timing Analysis, Signal Integrity, Viewdraw

SPRTG: Hardware Engineer (ASIC/FPGA Design Verification Engineer)

Job Description:
Participate in architecture and design verification of complex networking ASIC. Responsibilities include:
- Architecture/Micro-Architecture definition
- Standalone and Integrated functional verification;
- Documentation and review of Verification architecture and testplans
- Develop verification environment (models, checkers, packet manager) using Specman/Vera
- Develop random, pseudo-random and directed tests
- Establish verification effectiveness using assertion/functional/code coverage and code reviews
- RTL and gates simulation, debug and root cause
- Regression triage and debug
- Formal verification and equivalence checking.
- Lab debug and design validation

Skills required:
- Prior significant verification experience on complex ASICs.
- Good background in networking concepts.
- Experience with Vera/Specman and Verilog.
- Chip and system and test experience.
- Programming and scripting skills.
- Good planning skills (well partioned designs, well organized code)
- Outstanding written and verbal communication skills
- Capability of critical thinking, challenging design intent

Education:
MSEE with 5+ yrs or BSEE/CS with 7+ yrs relevant experience

DSBU: Mechanical Engineer

Job Description Skills Required
Assumes a complex role on project team involving the entire system packaging process. Assists in the design and documentation of computer enclosures and related electro-mechanical assemblies using solids modeling techniques. Conceptualizes, plans and executes the design and development of switch packaging products. Consults with cross-functional groups for product requirements, definitions and design. Defines, directs and participates in the design verification and testing of new products. my.chinahrlab.com
- Direct electronics industry experience, skilled in the art and science of electronics packaging at the board, box and rack level.
- Selects electro-mechanical components such as air movers, heatsinks and complex interconnection systems. Determines form factors, raw materials, finishes and manufacturing processes.
- Proficiency in developing conceptual and production designs using UG NX and Ideas SDRC 3-D solids modeling software, 4000hr plus of recent experience.
- Has experience in the design and development of tooling for high volume sheet metal, plastic and die casting.

Software: Maxwell 3D

Description: 3D electrostatic, magnetostatic, and low-frequency magnetic finite element analysis codes.

Software: Ansoft HFSS

Description : 3D full-wave finite element code

Software: Maxwell Eminence

Description: electrostatic, magnetostatic and quasi-static field analysis and full-wave field simulation codes employing the finite element method and the boundary element method.

Software: Microwave Explorer

Description: 3D planar moment method for MMIC and hybrid circuit design.

Software: Serenade

Description: This is an integrated software suite for all high frequency circuit and system designs such as RF and microwave. It is applicable for the following levels of analysis: circuit, system, electromagnetic simulation, and the physical design.

3. Applied Simulation Technology

San Jose, CA

Phone: (408) 436-9070

FAX: (408) 436-9078

Software: ApsimRADIA

Description: ApsimRADIA can simultaneously simulate radiated emission noise and conducted transmission line noise. It considers the impact of interconnect technology, cabling, packaging, and enclosure design on EMI. ApsimRADIA can predict both differential and common mode radiated emissions. Both types of EMI have a strong dependency on the physical design itself. Therefore accurate modeling tools to convert the physical entities into electrical properties are the key to successfully predicting the emitted radiation. ApsimRADIA uses a variety of field solvers to accomplish this.

Software: ApsimRADIA-WB

Description: ApsimRADIA-WB is designed to evaluate the impact of electrical and physical characteristics on EMI. ApsimRADIA-WB accurately predicts the radiated emissions from PCB, MCM, cables and subsystems. As a result, the user can investigate EMI issues from a system point of view as well. This avoids designs that work on a board basis but fail at the system level. ApsimRADIA-WB is a complete solution incorporating schematic capture, field solvers and EMI simulators in a fully integrated system. As the schematic is entered, the x,y,z coordinates of the physical interconnects are passed. Interconnect models can be simple impedance or delay lines or more complicated transmission lines as extracted from the field solver. The electrical models likewise, can be simple voltage or current sources, or more complicated behavioral IBIS or even Spice transistor level models. A 3D graphical playback display confirms the design. Once the design is entered, it is automatically simulated using ApsimRADIA and ApsimSPICE. The results can be viewed graphically or in a text, report, form and may be compared against an EMI standard of choice. Pass/fail assignments are then made. ApsimRADIA-WB provides insight into EMI issues resulting from physical placement, electrical specifications, interconnects and physical entities such as connectors. Design rules and conclusions leading to better designs can then be made at the earliest stage possible. The user can enter the physical interconnect locations and simulate their effects from a schematic diagram point of view. At the schematic level, changes to the electrical parts, physical entities and locations can easily be made without complicated CAD tools. Interactions of the physical locations of parts and electrical specifications of the interconnects can be studied for adverse effects.

4. Applied Wave Research, Inc.

Redondo Beach, CA

Phone: (310) 370-2496

FAX: (310) 793-6500

Software: EMSight

Description: spectral-domain moment-method code for analyzing planar structures.

5. Bay Technology

Aptos, CA

Phone: (408) 688-8919

FAX: (408) 688-6435

Software: IE3D

Description: 3D Planar, Full Wave, Method of Moments Electromagnetic Simulation and Optimization software. Circuit parameters are extracted from the solved current distribution and saved in formats compatible with time and frequency domain circuit simulators.

Software: Fidelity

Description: FDTD Full 3D Electromagnetic Simulation Software.

6. EMS-Plus

Durham, NC

Software: EZ-EMC

Description: 3D, FDTD technique; time or frequency domain results. Features: Shielding Analysis , Gasket performance Analysis , Cavity and Shielded Box Resonance , Heat-sink emissions analysis , Grounding Analysis , Susceptibility Analysis , Board Emissions , Ferrite Filter Analysis , Antenna Applications , Test Site Analysis (OATS, GTEM, Anechoic Room, etc.), etc.

7. HyperLynx

Innoveda, Inc

Marlborough, MA

Phone: (800) 873-8439

Software: HyperSuite EXT

Description: HyperSuite includes LineSim (Pre-Layout signal integrity simulation), BoardSim (Post-Layout signal integrity simulation), plus EMC and Crosstalk Analysis. With the HyperSuite, users can address high-speed PCB problems throughout the design cycle, beginning at the earliest, architectural stages and moving through post-layout verification.

LineSim is a pre-layout signal integrity analysis tool. It provides the capability to investigate and plan for signal-integrity issues in the pre-routing design stages prior to PCB layout. Hypothetical interconnect scenarios may be entered in schematic editor. Then, a detailed signal-integrity analysis may be performed. Waveforms are displayed in an oscilloscope viewer. The EMC analysis option to LineSim adds a spectrum analyzer that predicts radiated emissions from pre-layout net topologies. The predicted radiation levels can be compared at every frequency to government or user-defined limits.

BoardSim is a post-layout signal-integrity analysis tool. It reads the information in an actual routed PCB layout and allows a designer to perform detailed signal integrity analysis based on the exact routing of a particular layout. For every net that is simulated, BoardSim automatically constructs an electromagnetic simulation model on a segment-by-segment and via-by-via basis. Analysis is available in both and interactive modes. BoardSim's EMC option is unique for post-layout verification in that it can predict radiation levels not only from PCB traces, but also from component packages. It does this without requiring any modeling information about the components' packages.

8. Pacific ESI

Artarmon, Australia

Phone: (02) 9906-3377

Software: PAM CEM 2000

Description: This software was developed to perform realistic and predictive EMC simulations for industries such as aeronautics, telecommunications, electronics, and automotive. It is designed to simulate EMC lab testing, ranging from EMI caused by internal equipment wiring up to susceptibility or immunity of on-board equipment to external aggressions, as well as electromagnetic radiation of large harness systems towards the external environment (electromagnetic pollution). Capabilities include: Signal propagation on circuit boards and along interconnects: signal integrity, cross-talk, reflection and transmission analysis, s-parameter extraction; Electromagnetic compatibility and interference (EMC/EMI) analysis; Near to far field transform for radiation and EMC / EMI applications; Total field / scattered field zones for external wave sources; Electric, magnetic, and current density field sources; Built-in lumped elements including resistors, capacitors, inductors and voltage sources.

9. Quantic EMC Inc.

Manitoba, Canada

Phone: (204) 942-4000

Software: the Quantic Engine - includes for signal integrity and EMC simulation, and for system level EMC simulation of PC boards, enclosures, and cables.

Description: Use for screening PCB layouts for crosstalk, ringing, time delays, overshoot, undershoot, settling time and noise margin violations. Locate high-emission regions and identify the nets that cause EMC violations. Simulate two-sided boards and multi-layer boards with split power and ground planes. allows an analysis of the effects upon radiated fields due to changes in single nets, groups of nets, entire printed circuit boards, and most importantly, complete systems combining boards, cabling and enclosures. This tool shows results relative to changes. It does not yield absolute field values for comparison to actual laboratory measurements.

10. Remcom Inc.

State College, PA

Phone: (814) 353-2986

Fax: (814) 353-2986

Software: XFDTD

Description: 3D full-wave Finite Difference Time Domain (FDTD) software allows users to decrease the cost and time required to bring new products to market by eliminating unnecessary generations of expensive physical prototypes. The simulation software provides for early evaluation in the design process without the need for actual fabrication. XFDTD is a full wave electromagnetic solver based on the Finite Difference Time Domain method. It is fully three- dimensional. CAD objects may be imported into XFDTD and combined and edited within XFDTD using the internal graphical editor. Plane wave excitation or voltage and current sources can be used to excite the structure. XFDTD has an extensive list of important features, including lumped loads, impedance, S parameters, near/far zone fields, antenna radiation and efficiency, SAR peak and averages, special materials, graphical display capabilities, and many others. Optional modules include multi-processor module, human body meshes, and 3D Solids and Layered CAD Importers.

11. SETH Corporation

Johnstown, PA

Phone: (814) 255-4417

Fax: (814) 255-3417

Software: EMIT

Description: This software combines method of moments (MOM) and finite difference time domain (FDTD) methods. It uses 2D and 3D models and incorporates a user friendly graphical interface. The Toolbox approach offers three calculating kernel applications and two graphical processors with a variety of supporting Tools.

12. Sigrity, Inc

Santa Clara, CA

Phone: (408) 260-9344

Software: SPEED2000

Description: SPEED2000 integrates circuit and transmission line simulations with a fast, special-purpose electromagnetic field solver that computes electromagnetic interactions in multi-layer chip packages and printed circuit boards. In SPEED2000, power and ground planes are not treated as ideal power and ground planes with fixed potentials. Electromagnetic interactions inside packages (such as package resonance, coupling between different components, as well as interactions between circuits and packages) are taken into account during simulations. Transient as well as spatial variations of voltages and currents on power and ground planes are all computed and can be easily visualized. Signal waveforms computed by SPEED2000 automatically contain the effects of power and ground voltage bounces. SPEED2000 is a versatile electrical simulation tool for the analysis and design of electronic packages including chip carriers and printed circuit boards. It is particularly effective to be used for, but not limited to, following applications: Computation of power and ground noise; Evaluation and design of power and ground distribution systems, including power and ground plane arrangement, and power and ground via/pin assignment; Determination of decoupling capacitor placement, including the number, values, and locations of decoupling capacitors; Identification of package resonance; Evaluation of electromagnetic coupling between different components; Evaluation of signal and noise waveforms at various locations; Evaluation of signal and noise spectrum at various locations; Determination of frequency-dependent port parameters of packages, such as port input impedances, S parameters, and transfer functions between different ports; Evaluation of electromagnetic radiation from packages and printed circuit boards.
. Introduction
The EMC design for the Printed Circuit Board has been a popular topic. Guidelines and tips for high-speed PCB designs could be found from numerous resources. When investigating EMI issues associated with circuit boards, many details such as clock frequencies, switching rates, rise/fall times, signal harmonics, data transfer rates, impedances, trace loading, and types and values of the various circuit components, should be taken into considerations. The physical layout of the PC board and its associated metallic components are important considerations. Special attention should be given to the placement and characteristics of signal source components, vias, traces, pads, board stack-up, shielded enclosures, connectors and cables. For example, as signal frequencies and clock/switching rates increase, PC board trace characteristics can become similar to those of transmission lines and radiators. A PC board trace or component can become an efficient antenna at a length as small as one twentieth of a wavelength. EMI/EMC problems may be approached at the component, PC board or enclosure levels. However, it is much more efficient to deal with these problems as close to the source or susceptible victim as possible. Therefore, attentions should be paid to PCB design and layout to help designers identify problems prior to actual fabrication of the equipment.
The following sections will discuss important aspects of the PCB design with concern of the EMC.

2. Traces at High Frequencies
At high frequencies, traces on a PCB act as a mono-pole or loop antennas. As known, differential-mode radiation is the electromagnetic radiation caused by currents consisting of harmonic frequency components flowing in a loop in the PCB. The radiation is proportional to the current loop area and the square of the frequency of the signal. Common-mode radiation is the electromagnetic radiation caused by current flowing in an unterminated trace (or terminated with a high input impedance device) and may require load terminating resistors to eliminate reflections. The radiation resembles that of a mono-pole antenna and the magnitude is proportional to the current per line length and frequency.
Unfortunately, the high frequency components of the fundamental (lowest frequency in a complex wave) radiate more readily because their shorter wavelengths are comparable to trace lengths, which act as antennas. Consequently, although the amplitude of the harmonic frequency components decreases as the frequency increases, the radiated frequency varies depending on the antennas/traces characteristics. For example, interference signals produced by computing devices tend to lie in the 10 to 300 MHz region.
At what speed should there be concern about wave propagation rather than just current in conductors? The rule is that transmission line effects become an important design consideration when the trace length approaches 1/7 of the wave-length of the signal being transported. If the system clock frequency is 300 MHz, the wavelength in FR4 is about 0.5 m.

3. Rise and Fall Time
Generally, the system clock is a repetition rate of a square wave pulse, and the pulse information of "1" or "0" is carried on the leading edge of the pulse. This edge must be permitted to rise or fall as quickly as possible. Frequency and the rise time of the signal are related by the relation:

where, TR and f are in nS and GHz, respectively. Table 1 shows the rise times and wavelengths for common high-speed IC's.
Table 1. Device rise times & wavelengths
IC Type
TTL Schottky ECL GaAs
Rise Time (nS) 6-9 2-3 .45-.75 .05-.20
Wavelength in free space (m) 6.8 2.5 .52 .086
Wavelength in FR4 (m) 3.1 1.2 .24 .04
For example, for ECL: frequency = 0.35 / 0.45 = 777 MHz. This translates to a wavelength of about 375 mm in free air or 175 mm in FR4 and 100 mm in ceramic. Therefore, if the trace length is more than 25 mm for PCB's fabricated from FR4, then the electromagnetic properties of the ECL signal and the transmission line effects should be considered. Usually, signal rise/fall time, instead of the signal clock frequency, determines the critical signal speed in a digital system. A steep rise/fall time may be slowed by loading the signal line with a damping resistor close to the source.

4. Characteristic Impedance
Fifty to eighty ohm characteristic impedance is often used in high-speed designs. Lower impedance values cause excessive dI/dt crosstalk and can double the power consumed to create a heat dissipation problem. Higher impedances not only produce high crosstalk, but also produce circuits with greater EMI sensitivity and emission. Table 2 illustrates the effect that physical properties have on the impedance (ZO) of a transmission line.
Table 2. Effects of physical properties on impedance
Variable Impedance
Increase trace width Lower
Increase proximity of traces Higher
Increase signal/plane spacing Higher
Increase dielectric constant Lower
The fields emanating from the surface of a conventional single/double-sided board are not guided by a controlled return conductor (i.e. reference plane). Rather, the fields tend to terminate on adjacent traces, which creates crosstalk. Some of these fields escape the surface of the PCB totally and radiate outward. However, multilayer PCB's have ground and power distribution conductors embedded as planes in the substrate. The return currents for the signal traces flow through the reference plane, which is in close proximity to the trace. Also, the use of planes provides the low impedance power distribution necessary for good supply decoupling.
Enclosing signal traces between the ground and power planes provides a shield which reduces both radiation (by up to 45 dB) and susceptibility to radiation, as well as providing ESD protection. It is a good practice to route high speed, fast rise time signals between these planes to eliminate radiation. If a large capacitance exists between the rails, both ground and power planes may be used as reference planes. It has been found that there is up to 20 dB greater emissions from edge-located traces compared to traces located in the center of the board on outer layers. However, there is no change as the traces were placed nearer the PCB edges.

5. Clocks
Clock circuits have the highest toggle rates of all circuits and are the primary source of noise generated in digital circuits. Clock timing and skew are critical factors affecting circuit performance. It is best to centrally locate the clock generator and distribute it radially. Radiated fields from the outward flowing currents tend to cancel, which reduces and synchronises propagation delays throughout the board. Equal mark-to-space ratios with controlled rise/fall times also help reduce noise by removing even harmonics.
In high-speed systems, the clock cycle time is usually shorter than the propagation delay for a signal to travel from one device to another. For the system to perform correctly at high speeds, a well-controlled propagation time is required, and adjustments in the timing skew for some signals may be necessary. Tuned delay can be achieved with the aid of software. Alternatively, trace lengths can be equalised manually to avoid skew by using a star routing pattern from the source.
Component Density = Trace Density = Crosstalk
Generally, an assembly is populated as densely as possible with surface mounted devices (SMD) to minimize the size of the board and reduce propagation time. The result is, of course, that traces must run close to each other, which creates crosstalk. Crosstalk is the transfer of pulse energy by the electromagnetic field from a source line to a victim line. The intensity of the coupled signal decreases with shorter adjacent line segments, wider line separations, lower line impedance and longer pulse rise times. Field solver software is recommended to predict transmission line characteristic impedances, propagation velocities and crosstalk. As clock speeds increase, this may become mandatory. To accurately estimate delays and crosstalk, a layer stack-up must be coupled with the field solver. The result is a quick and accurate characterization of the layout traces that is dynamically updated on the fly. Note that the dielectric constant of FR4 material can vary by as much as 20%.

6. Logic Families
Mixing logic families is not advised because of their differences in voltage swings, noise margins and logic levels. For example, Schottky TTL swings 3 V while the ECL family has only 100 mV DC noise margin. Mixing these two logic families could cause significant undesired coupling. For high-speed devices, switching activity is accompanied by equally high-speed demands for changes in current from the power supply. If several devices are switching at the same instant, the power distribution system must be able to supply the current while maintaining the supply voltage within the specified limits. Low inductance supply connections to the devices (one of the many advantages of SMD) and high capacitance distributed across the board reduces the problem.

7. Filtering and Bypassing
EMI filters can be used as a shunt element to divert electrical currents from a trace or conductor; as a series element to block a trace or conductor current; or they may be used as a combination of these functions. Selection of the filter elements should always be based on the desired frequency range and component characteristics. A low pass filter can be useful for reducing most high frequency EMI problems. It incorporates a capacitive shunt and series resistance or inductance. However, at frequency extremes, the capacitor can become inductive and the inductor can become capacitive causing the filter to act more like a band-stop filter. The filter design type should be based on the overall impedance at the circuit ’s point of application for proper match. A T-filter design is effective for most EMI applications and is ideal for analog and digital I/O ports.
Capacitors may be used for signal filtering and power source decoupling within their high frequency performance characteristics. However, their internal and external inductance can limit performance at high frequencies. Ceramic capacitors are recommended for the high frequencies, particularly those in the GHz range. A capacitor providing a reactance of less than 1 Ohm at the frequency of concern should suffice. Capacitor lead and trace lengths must be short at the high frequencies in order to prevent the addition of inductive reactance.
PC board bypass capacitors used at high frequencies (greater than 100 MHz) should utilize surface mount technology (SMT) with vias close enough to the mounting pad to minimize or eliminate the traces. The via holes should be large (greater than .035 inch in diameter) and the PC board should be thin enough to bring power and ground planes near the body of the capacitor (less than .030 inch thick). Proper design layout of the bypass capacitors can greatly reduce the power and ground circuit noise by lowering the overall effective inductance of the capacitors.

8. Decoupling
Decoupling capacitors provide current to devices until a power supply can respond. High frequency switching, composing a broad spectrum of current frequencies, requires several low to high frequency capacitors. This requirement is because a single capacitor typically cannot provide such a broad frequency.
A chip capacitor should be located as close as possible to a device's supply pins. To reduce series inductance the capacitor lands should be connected to the power pins using a trace width of at least 20 mil. To prevent common-mode noise, keep the trace as short as possible and do not connect directly to the plane via a thermal relief.
Tantalum capacitors (e.g. 10 uF) should be spaced evenly across the board, generally, one for every six or so ICs. These tantalum's provide current for the low frequency component of the switching transient.

9. Mixed Signals and Split Planes
When both analogue and digital devices are used on the same PCB, partitioning the ground plane is usually necessary. The components should be positioned so that all the devices are grouped in such a way that no digital signals will cross over the analog ground and no analog signals will cross over the digital ground.
Split or isolated planes can be used to effectively force the current associated with a particular circuit into a specific area that can be decoupled or grounded. The split plane confines high frequency currents and return paths so they can not flow across or through adjacent low frequency circuits, preventing crosstalk.

10. Shielding and Large Components
Large PQFP's typically require installation in a shielded equipment enclosure for compliance. However, the same piece of silicon housed in a PGA or BGA package may achieve compliance. The PGA and BGA packages have an efficient heatsink on the top of the package, which not only serves to dissipate the heat, but also acts as an EMI shield.

11. Routing
Orthogonal trace corners should be avoided. The debate rages, but as frequencies and edge rates continue to rise, ninety degree corners introduce excess capacitance and cause a small change in characteristic impedance. This becomes disastrous at high frequencies (e.g. 100 MHz) when electrons virtually fly off the sharp corners of the bend. Forty-five degree turns, with a minimum segment length of twice the trace width, are better. Arced corners, with the inside radius of at least the trace width, are by far the best approach for high-speed signals.
Use multi-layer PC boards rather than single-layer boards whenever possible. If a single layer board must be used, a ground plane should be utilized to help reduce radiation. Top and bottom ground planes can help reduce radiation from multi-layer boards by at least 10 dB. Segmented PC board ground planes are useful for reducing cable radiation due to common mode currents. Power and return planes should be located on opposite sides of a multi-layer PCB. Effective power planes are low in inductance. Therefore, any transients that may develop on the power planes will be at lower levels, resulting in lower common mode EMI.
Connection of the power planes to high frequency IC power pins should be as close to the IC pins as possible. Faster rise times may require connections directly to the pads of the IC power pins. Analog and digital circuits are susceptible to interaction when located in close proximity to each other. These should be located on different layers of the PC board whenever possible. If the circuits must be located on the same layer, they should be separated into analog and digital areas with proper isolation layout. High frequency traces, such as those used for clock and oscillator circuits, should be contained by two ground planes. This provides for maximum isolation. The reactance of a trace or conductor can easily exceed its dc resistance as frequency increases. If this trace is run close to its ground plane, the inductance can be reduced by about one third. Additional EMI preventive measures for clock/oscillator traces include the utilization of guard traces grounded to the ground plane at several locations. The shielding of clock and oscillator components with foil or small metallic enclosures may also be needed.

--------------------------------------------------------------------------------

28.2.2007 > SCHURTER Spotlights its Smallest Fuse for Secondary Overcurrent Protection

Lucerne - December, 2006 - SCHURTER released the electronic chip fuse USF 0402 which offers very quick-acting characteristic with rated current values up to 5 A. The low voltage drop generates less heat dissipation in contrast to competitor products. The current rating range reaches from 0.375 to 5.0 A with voltage ratings of 32 VDC up to 4.0 A, which is unique in the market and 24 VDC for the 5 A rating. The device provides a breaking capacity of 35 A at rated voltages and an operating temperature range of -55 8? € C to +125 8? € C .The fuse is designed to provide secondary overcurrent protection on systems using DC power sources of up to 32 VDC. Target applications are laptops, multimedia devices, cell phones, and other portable electronics, providing optimal performance in an extremely small package size 0402 (1.05 mm by 0.55 mm by 0.475 mm).The legend marking on each fuse allows visual identification. The fuse is UL approved and carries cURus approval and holds a Free of CCC certificate.The device is RoHS compliant and is supplied on tape either with 1k or 5k or 15k pieces.

Top data sheet

--------------------------------------------------------------------------------

2.11.2006 > Smallest Fuse Approved for Use in Space Applications
SMD Fuse for Space Applications is Approved according to ESA/SCC

SCHURTER's new SMD-fuse type MGA-S meets the standard of ESA/SCC Generic Specification No 4008 for space applications.

Based on the design of Schurter's existing MGA, the new version meets the requirements of the space industry and its demands for a fuse product with hermetic seal and robust construction, such that with a disconnection, no arcs or gasses can escape. The requirements also include additional pre-arcing times, consistency of over-current disconnects at rated voltage regardless of vacuum conditions, stable derating curves at higher ambient temperatures, and durability against mechanical vibration and shock.

The technology widely used for standard fuses today is not able to fulfil the requirements for a long-term reliability of 20 to 30 years. This long-term stability is influenced by leakage loss, ageing and ambient temperature in combination with thermal cycles, which are quite prevalent in satellite applications. This is mainly due to the ageing phenomena of the traditional tinned fuse links. The MGA-S with its thin film technology (metal sputter process) increases the long-term stability of the fuse through the homogeneous crystal structure of the metal layers.

Its small dimensions in a popular 1206 footprint [3.2 mm by 1.55 mm] make the MGA-S the smallest SMD fuse qualified for use in equipment for space. Applications include equipment that is launched into orbit with a specific focus on satellite power system architectures operating up to 125 VDC in vacuum environments. This includes protection of power supplies, batteries and solar arrays.

The MGA-S is the only European manufactured SMD fuse for space applications. It is built according to UL 248-14 and CSA 22.2 no. 248-14 and carries UL and CSA recognition. It is also tested according to Mil-Std 202, Method 108A, 103B, 106E, 107D, 211A & 215A.

In-Circuit Test
In-Circuit Test (ICT) is a powerful tool in the automated testing of PCB. ICT uses the circuit nodes of a board to measure the performance of components regardless if other components are connected to them. Resistance, capacitance, inductance and others, can be measured for components and the connections between them.

Since most PCB problems are due to manufacturing reasons, ICT looks for the typical issues like short circuits, open circuits, and incorrect components. An in-circuit test does not test the functionality of a board, but test many of the components that make up the board.

Advantech has years of experience programming and using state-of-the-art ICT equipment as well as building the fixtures used for testing specific boards. Once fixtures are made and the equipment is programmed, the results provide immediate information that can be used by a range of technicians to quickly check and control design and quality.

In-Circuit Test Benefits Include:
Automated board testing
Catch design mistakes
Catch manufacturing issues
Easy to interpret test results